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[Qemu-devel] [PATCH 06/18] tcg/arm: add defines for the allowed instruct
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 06/18] tcg/arm: add defines for the allowed instructions set |
Date: |
Wed, 7 Apr 2010 19:51:13 +0200 |
Use a set of #define to define the allowed ARM instructions, depending
on the __ARM_ARCH_*__ GCC defines.
Signed-off-by: Aurelien Jarno <address@hidden>
---
tcg/arm/tcg-target.c | 27 ++++++++++++++++++++++++---
1 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index ee5f723..cae6385 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -22,6 +22,27 @@
* THE SOFTWARE.
*/
+#if defined(__ARM_ARCH_5T__) || \
+ defined(__ARM_ARCH_5TE__) || \
+ defined(__ARM_ARCH_5TEJ__) || \
+ defined(__ARM_ARCH_6__) || \
+ defined(__ARM_ARCH_7A__) || \
+ defined(__ARM_ARCH_7__)
+# define USE_ARMV5_INSTRUCTIONS 1
+#endif
+
+#if defined(__ARM_ARCH_6__) || \
+ defined(__ARM_ARCH_7A__) || \
+ defined(__ARM_ARCH_7__)
+# define USE_ARMV6_INSTRUCTIONS 1
+#endif
+
+#if defined(__ARM_ARCH_7A__) || \
+ defined(__ARM_ARCH_7__)
+# define USE_ARMV7_INSTRUCTIONS 1
+#endif
+
+
#ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"%r0",
@@ -361,7 +382,7 @@ static inline void tcg_out_movi32(TCGContext *s,
tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :
tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);
-#ifdef __ARM_ARCH_7A__
+#ifdef USE_ARMV7_INSTRUCTIONS
/* use movw/movt */
/* movw */
tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
@@ -1433,7 +1454,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
break;
case INDEX_op_ext8s_i32:
-#ifdef __ARM_ARCH_7A__
+#ifdef USE_ARMV7_INSTRUCTIONS
/* sxtb */
tcg_out32(s, 0xe6af0070 | (args[0] << 12) | args[1]);
#else
@@ -1444,7 +1465,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
#endif
break;
case INDEX_op_ext16s_i32:
-#ifdef __ARM_ARCH_7A__
+#ifdef USE_ARMV7_INSTRUCTIONS
/* sxth */
tcg_out32(s, 0xe6bf0070 | (args[0] << 12) | args[1]);
#else
--
1.7.0.4
- [Qemu-devel] [PATCH 0/18] tcg/arm: cleanup and improvements, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 02/18] tcg/arm: explicitely list clobbered/reserved regs, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 01/18] tcg/arm: remove SAVE_LR code, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 05/18] tcg/arm: align 64-bit arguments in function calls, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 09/18] tcg/arm: add rotation ops, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 07/18] tcg/arm: sxtb and sxth are available starting with ARMv6, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 11/18] tcg/arm: add bswap ops, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 08/18] tcg/arm: use the blx instruction when possible, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 06/18] tcg/arm: add defines for the allowed instructions set,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 03/18] tcg/arm: remove store signed functions, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 04/18] tcg/arm: replace integer values by registers enum, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 18/18] tcg/arm: don't try to load constants using pc, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 13/18] tcg/arm: use ext* ops in qemu_ld, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 10/18] tcg/arm: add ext16u op, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 16/18] tcg/arm: fix argument alignment in qemu_st64, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 17/18] tcg/arm: optimize register allocation order, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 14/18] tcg/arm: bswap arguments in qemu_ld/st if needed, Aurelien Jarno, 2010/04/07