[Qemu-devel] [PATCH 6/6] tcg-sparc: Implement ORC.

[Richard Henderson]

Signed-off-by: Richard Henderson <address@hidden>
---
 tcg/sparc/tcg-target.c |    5 +++++
 tcg/sparc/tcg-target.h |    2 ++
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index c1761cc..e8bbcdc 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1115,6 +1115,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, 
const TCGArg *args,
     OP_32_64(or):
         c = ARITH_OR;
         goto gen_arith;
+    OP_32_64(orc):
+        c = ARITH_ORN;
+        goto gen_arith;
     OP_32_64(xor):
         c = ARITH_XOR;
         goto gen_arith;
@@ -1319,6 +1322,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_and_i32, { "r", "r", "rJ" } },
     { INDEX_op_andc_i32, { "r", "r", "rJ" } },
     { INDEX_op_or_i32, { "r", "r", "rJ" } },
+    { INDEX_op_orc_i32, { "r", "r", "rJ" } },
     { INDEX_op_xor_i32, { "r", "r", "rJ" } },
 
     { INDEX_op_shl_i32, { "r", "r", "rJ" } },
@@ -1374,6 +1378,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_and_i64, { "r", "r", "rJ" } },
     { INDEX_op_andc_i64, { "r", "r", "rJ" } },
     { INDEX_op_or_i64, { "r", "r", "rJ" } },
+    { INDEX_op_orc_i64, { "r", "r", "rJ" } },
     { INDEX_op_xor_i64, { "r", "r", "rJ" } },
 
     { INDEX_op_shl_i64, { "r", "r", "rJ" } },
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 4ea0c19..dc68787 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -94,6 +94,7 @@ enum {
 #define TCG_TARGET_HAS_neg_i32
 #define TCG_TARGET_HAS_not_i32
 #define TCG_TARGET_HAS_andc_i32
+#define TCG_TARGET_HAS_orc_i32
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_ext32s_i64
@@ -101,6 +102,7 @@ enum {
 #define TCG_TARGET_HAS_neg_i64
 #define TCG_TARGET_HAS_not_i64
 #define TCG_TARGET_HAS_andc_i64
+#define TCG_TARGET_HAS_orc_i64
 #endif
 
 //#define TCG_TARGET_HAS_bswap32_i32
-- 
1.6.2.5