[Qemu-devel] Re: [PATCH 06/11] pci: use pci_regs.h

[Michael S. Tsirkin]

On Mon, Dec 14, 2009 at 09:48:21PM +0900, Isaku Yamahata wrote:
> include pci_regs.h and remove duplicated defines.
> 
> Signed-off-by: Isaku Yamahata <address@hidden>

Good stuff.
Acked-by: Michael S. Tsirkin <address@hidden>

> ---
>  hw/pci.h |   72 ++-----------------------------------------------------------
>  1 files changed, 3 insertions(+), 69 deletions(-)
> 
> diff --git a/hw/pci.h b/hw/pci.h
> index 91f3809..b5e7abb 100644
> --- a/hw/pci.h
> +++ b/hw/pci.h
> @@ -94,76 +94,10 @@ typedef struct PCIIORegion {
>  #define PCI_ROM_SLOT 6
>  #define PCI_NUM_REGIONS 7
>  
> -/* Declarations from linux/pci_regs.h */
> -#define PCI_VENDOR_ID                0x00    /* 16 bits */
> -#define PCI_DEVICE_ID                0x02    /* 16 bits */
> -#define PCI_COMMAND          0x04    /* 16 bits */
> -#define  PCI_COMMAND_IO              0x1     /* Enable response in I/O space 
> */
> -#define  PCI_COMMAND_MEMORY  0x2     /* Enable response in Memory space */
> -#define  PCI_COMMAND_MASTER  0x4     /* Enable bus master */
> -#define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
> -#define PCI_STATUS              0x06    /* 16 bits */
> -#define  PCI_STATUS_INTERRUPT   0x08
> -#define PCI_REVISION_ID         0x08    /* 8 bits  */
> -#define PCI_CLASS_PROG               0x09    /* Reg. Level Programming 
> Interface */
> -#define PCI_CLASS_DEVICE        0x0a    /* Device class */
> -#define PCI_CACHE_LINE_SIZE  0x0c    /* 8 bits */
> -#define PCI_LATENCY_TIMER    0x0d    /* 8 bits */
> -#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
> -#define  PCI_HEADER_TYPE_NORMAL              0
> -#define  PCI_HEADER_TYPE_BRIDGE              1
> -#define  PCI_HEADER_TYPE_CARDBUS     2
> +#include "pci_regs.h"
> +
> +/* PCI HEADER_TYPE */
>  #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
> -#define PCI_BASE_ADDRESS_0   0x10    /* 32 bits */
> -#define  PCI_BASE_ADDRESS_SPACE_IO   0x01
> -#define  PCI_BASE_ADDRESS_SPACE_MEMORY       0x00
> -#define  PCI_BASE_ADDRESS_MEM_TYPE_64        0x04    /* 64 bit address */
> -#define  PCI_BASE_ADDRESS_MEM_PREFETCH       0x08    /* prefetchable? */
> -#define PCI_PRIMARY_BUS              0x18    /* Primary bus number */
> -#define PCI_SECONDARY_BUS    0x19    /* Secondary bus number */
> -#define PCI_SUBORDINATE_BUS  0x1a    /* Highest bus number behind the bridge 
> */
> -#define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
> -#define PCI_IO_LIMIT            0x1d
> -#define  PCI_IO_RANGE_TYPE_32        0x01
> -#define  PCI_IO_RANGE_MASK      (~0x0fUL)
> -#define PCI_SEC_STATUS               0x1e    /* Secondary status register, 
> only bit 14 used */
> -#define PCI_MEMORY_BASE         0x20    /* Memory range behind */
> -#define PCI_MEMORY_LIMIT        0x22
> -#define  PCI_MEMORY_RANGE_MASK  (~0x0fUL)
> -#define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind 
> */
> -#define PCI_PREF_MEMORY_LIMIT   0x26
> -#define  PCI_PREF_RANGE_MASK    (~0x0fUL)
> -#define  PCI_PREF_RANGE_TYPE_64 0x01
> -#define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory 
> range */
> -#define PCI_PREF_LIMIT_UPPER32       0x2c
> -#define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
> -#define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */
> -#define PCI_ROM_ADDRESS              0x30    /* Bits 31..11 are address, 
> 10..1 reserved */
> -#define  PCI_ROM_ADDRESS_ENABLE      0x01
> -#define PCI_IO_BASE_UPPER16     0x30    /* Upper half of I/O addresses */
> -#define PCI_IO_LIMIT_UPPER16    0x32
> -#define PCI_CAPABILITY_LIST  0x34    /* Offset of first capability list 
> entry */
> -#define PCI_ROM_ADDRESS1     0x38    /* Same as PCI_ROM_ADDRESS, but for 
> htype 1 */
> -#define PCI_INTERRUPT_LINE   0x3c    /* 8 bits */
> -#define PCI_INTERRUPT_PIN    0x3d    /* 8 bits */
> -#define PCI_MIN_GNT          0x3e    /* 8 bits */
> -#define PCI_BRIDGE_CONTROL      0x3e
> -#define PCI_MAX_LAT          0x3f    /* 8 bits */
> -
> -/* Capability lists */
> -#define PCI_CAP_LIST_ID              0       /* Capability ID */
> -#define PCI_CAP_LIST_NEXT    1       /* Next capability in the list */
> -
> -#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
> -
> -/* Bits in the PCI Status Register (PCI 2.3 spec) */
> -#define PCI_STATUS_RESERVED1 0x007
> -#define PCI_STATUS_INT_STATUS        0x008
> -#define PCI_STATUS_CAP_LIST  0x010
> -#define PCI_STATUS_66MHZ     0x020
> -#define PCI_STATUS_RESERVED2 0x040
> -#define PCI_STATUS_FAST_BACK 0x080
> -#define PCI_STATUS_DEVSEL    0x600
>  
>  #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
>                  PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
> -- 
> 1.6.5.4