[Qemu-devel] [PATCH 01/11] target-mips: add ISAMode bits for mips16 execution

[Nathan Froyd]

Signed-off-by: Nathan Froyd <address@hidden>
---
 target-mips/cpu.h       |    1 +
 target-mips/translate.c |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 82f9a38..e8febe6 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -167,6 +167,7 @@ struct TCState {
     target_ulong CP0_TCContext;
     target_ulong CP0_TCSchedule;
     target_ulong CP0_TCScheFBack;
+    uint32_t ISAMode; /* MIPS32 or MIPS16 mode */
     int32_t CP0_Debug_tcstatus;
 };
 
diff --git a/target-mips/translate.c b/target-mips/translate.c
index e9d9224..b0a1b29 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -463,6 +463,7 @@ typedef struct DisasContext {
     struct TranslationBlock *tb;
     target_ulong pc, saved_pc;
     uint32_t opcode;
+    int isa_mode;
     int singlestep_enabled;
     /* Routine used to access memory */
     int mem_idx;
@@ -8306,6 +8307,7 @@ gen_intermediate_code_internal (CPUState *env, 
TranslationBlock *tb,
     ctx.pc = pc_start;
     ctx.saved_pc = -1;
     ctx.singlestep_enabled = env->singlestep_enabled;
+    ctx.isa_mode = env->active_tc.ISAMode;
     ctx.tb = tb;
     ctx.bstate = BS_NONE;
     /* Restore delay slot state from the tb context.  */
-- 
1.6.3.2