qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH 4/7] kvm: Add sanity checks to slot management


From: Hollis Blanchard
Subject: Re: [Qemu-devel] [PATCH 4/7] kvm: Add sanity checks to slot management
Date: Wed, 29 Apr 2009 12:10:00 -0500

On Wed, 2009-04-29 at 12:38 +0200, Jan Kiszka wrote:
> Liu Yu-B13201 wrote:
> > 
> >> -----Original Message-----
> >> From: address@hidden 
> >> [mailto:address@hidden 
> >> On Behalf Of Jan Kiszka
> >> Sent: Sunday, April 12, 2009 1:20 AM
> >> To: address@hidden
> >> Subject: [Qemu-devel] [PATCH 4/7] kvm: Add sanity checks to 
> >> slot management
> >>
> >> Fail loudly if we run out of memory slot.
> >>
> >> Make sure that dirty log start/stop works with consistent 
> >> memory regions
> >> by reporting invalid parameters. This reveals several 
> >> inconsistencies in
> >> the vga code, patch to fix them follows later in this series.
> >>
> >> And, for simplicity reasons, also catch and report unaligned memory
> >> regions passed to kvm_set_phys_mem (KVM works on page basis).
> >>
> > 
> > Commit d3f8d37fe2d0c24ec8bac9c94d5b0e2dc09c0d2a hurts kvm/powerpc
> > The alignment check in kvm_set_phys_mem prevents pci controller and mpic 
> > initializing mmio regions.
> 
> What is the alignment of those regions then? None? And do regions of
> different types overlap even on the same page? Maybe the check reveals
> some deeper conflict /wrt KVM. Can you point me to the involved code files?

These PCI controllers make separate calls to
cpu_register_physical_memory() for separate callbacks. Reading
ppce500_pci_init(), for example:
0xe0008000 -> CFGADDR (4 bytes)
0xe0008004 -> CFGDATA (4 bytes)
0xe0008c00 -> other registers

The loop in cpu_register_physical_memory_offset() handles "subpage"
registration. However, kvm_set_phys_mem() is called outside that loop,
so it gets the non-page-aligned addresses.

-- 
Hollis Blanchard
IBM Linux Technology Center





reply via email to

[Prev in Thread] Current Thread [Next in Thread]