[Qemu-devel] [PATCH 4/4] create TCG slots for registers based on CPU

[Nathan Froyd]

There's no point in creating floating-point registers if the chip we're
emulating doesn't have them.  Likewise for Altivec and SPE registers.

Signed-off-by: Nathan Froyd <address@hidden>
---
 target-ppc/translate.c |   52 +++++++++++++++++++++++++++--------------------
 1 files changed, 30 insertions(+), 22 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 412c8d0..8170718 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -104,36 +104,42 @@ void ppc_translate_init(const ppc_def_t *def)
                                         offsetof(CPUState, gpr[i]), p);
         p += (i < 10) ? 3 : 4;
 #if !defined(TARGET_PPC64)
-        sprintf(p, "r%dH", i);
-        cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, gprh[i]), p);
-        p += (i < 10) ? 4 : 5;
+        if (def->insns_flags & PPC_SPE) {
+            sprintf(p, "r%dH", i);
+            cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
+                                                 offsetof(CPUState, gprh[i]), 
p);
+            p += (i < 10) ? 4 : 5;
+        }
 #endif
 
-        sprintf(p, "fp%d", i);
-        cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
-                                            offsetof(CPUState, fpr[i]), p);
-        p += (i < 10) ? 4 : 5;
+        if (def->insns_flags & PPC_FLOAT) {
+            sprintf(p, "fp%d", i);
+            cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
+                                                offsetof(CPUState, fpr[i]), p);
+            p += (i < 10) ? 4 : 5;
+        }
 
-        sprintf(p, "avr%dH", i);
+        if (def->insns_flags & PPC_ALTIVEC) {
+            sprintf(p, "avr%dH", i);
 #ifdef WORDS_BIGENDIAN
-        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, 
avr[i].u64[0]), p);
+            cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
+                                                 offsetof(CPUState, 
avr[i].u64[0]), p);
 #else
-        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, 
avr[i].u64[1]), p);
+            cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
+                                                 offsetof(CPUState, 
avr[i].u64[1]), p);
 #endif
-        p += (i < 10) ? 6 : 7;
+            p += (i < 10) ? 6 : 7;
 
-        sprintf(p, "avr%dL", i);
+            sprintf(p, "avr%dL", i);
 #ifdef WORDS_BIGENDIAN
-        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, 
avr[i].u64[1]), p);
+            cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
+                                                 offsetof(CPUState, 
avr[i].u64[1]), p);
 #else
-        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, 
avr[i].u64[0]), p);
+            cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
+                                                 offsetof(CPUState, 
avr[i].u64[0]), p);
 #endif
-        p += (i < 10) ? 6 : 7;
+            p += (i < 10) ? 6 : 7;
+        }
     }
 
     cpu_nip = tcg_global_mem_new(TCG_AREG0,
@@ -154,8 +160,10 @@ void ppc_translate_init(const ppc_def_t *def)
     cpu_reserve = tcg_global_mem_new(TCG_AREG0,
                                      offsetof(CPUState, reserve), "reserve");
 
-    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
-                                       offsetof(CPUState, fpscr), "fpscr");
+    if (def->insns_flags & PPC_FLOAT) {
+        cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
+                                           offsetof(CPUState, fpscr), "fpscr");
+    }
 
     cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
                                              offsetof(CPUState, access_type), 
"access_type");
-- 
1.6.0.5