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[Qemu-devel] [PATCH 02/24] Fix cpu_physical_memory_rw when operating on
From: |
Tristan Gingold |
Subject: |
[Qemu-devel] [PATCH 02/24] Fix cpu_physical_memory_rw when operating on IO blocks. |
Date: |
Fri, 13 Mar 2009 15:20:21 +0100 |
In some cases, addr was destroyed and the next access was wrong. This
occured while making 64bits IO accesses.
Signed-off-by: Tristan Gingold <address@hidden>
---
exec.c | 26 +++++++++++++++-----------
1 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/exec.c b/exec.c
index fd3e441..76a89ca 100644
--- a/exec.c
+++ b/exec.c
@@ -357,16 +357,16 @@ static PhysPageDesc
*phys_page_find_alloc(target_phys_addr_t index, int alloc)
/* Level 2..n-1 */
for (i = (L1_SHIFT / L2_BITS) - 1; i > 0; i--) {
- p = *lp;
- if (!p) {
- /* allocate if not found */
- if (!alloc)
- return NULL;
- p = qemu_vmalloc(sizeof(void *) * L2_SIZE);
- memset(p, 0, sizeof(void *) * L2_SIZE);
- *lp = p;
- }
- lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
+ p = *lp;
+ if (!p) {
+ /* allocate if not found */
+ if (!alloc)
+ return NULL;
+ p = qemu_vmalloc(sizeof(void *) * L2_SIZE);
+ memset(p, 0, sizeof(void *) * L2_SIZE);
+ *lp = p;
+ }
+ lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
}
#else
p = (void **)l1_phys_map;
@@ -2987,6 +2987,7 @@ void cpu_physical_memory_rw(target_phys_addr_t addr,
uint8_t *buf,
target_phys_addr_t page;
unsigned long pd;
PhysPageDesc *p;
+ unsigned long addr1;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
@@ -3006,6 +3007,8 @@ void cpu_physical_memory_rw(target_phys_addr_t addr,
uint8_t *buf,
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
+ else
+ addr1 = addr;
/* XXX: could force cpu_single_env to NULL to avoid
potential bugs */
if (l >= 4 && ((addr1 & 3) == 0)) {
@@ -3025,7 +3028,6 @@ void cpu_physical_memory_rw(target_phys_addr_t addr,
uint8_t *buf,
l = 1;
}
} else {
- unsigned long addr1;
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
/* RAM case */
ptr = phys_ram_base + addr1;
@@ -3046,6 +3048,8 @@ void cpu_physical_memory_rw(target_phys_addr_t addr,
uint8_t *buf,
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
+ else
+ addr1 = addr;
if (l >= 4 && ((addr1 & 3) == 0)) {
/* 32 bit read access */
val = io_mem_read[io_index][2](io_mem_opaque[io_index],
addr1);
--
1.6.2
- [Qemu-devel] [PATCH 0/24]: add alpha es40 system emulation, Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 01/24] Add support for multi-level phys map., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 02/24] Fix cpu_physical_memory_rw when operating on IO blocks.,
Tristan Gingold <=
- [Qemu-devel] [PATCH 03/24] Fix bug: palcode is at least 6 bits., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 04/24] Fix bug: do not mask address LSBs for ldwu., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 05/24] bug fix: avoid nop to override next instruction, Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 06/24] Be slightly more verbose for unassigned_mem_read*, Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 07/24] Increase Alpha physical address size to 44 bits., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 08/24] Allow 5 mmu indexes., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 09/24] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 10/24] Add square wave output support., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 11/24] Add ali1543 super IO pci device., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 12/24] Add 21272 chipset (memory and pci controller for alpha), Tristan Gingold, 2009/03/13