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[Qemu-devel] [PATCH 41/42] target-ppc: add {l, st}ve{b, h, w}x instructi
From: |
Nathan Froyd |
Subject: |
[Qemu-devel] [PATCH 41/42] target-ppc: add {l, st}ve{b, h, w}x instructions. |
Date: |
Sun, 14 Dec 2008 18:15:14 -0800 |
Signed-off-by: Nathan Froyd <address@hidden>
---
target-ppc/helper.h | 6 ++++++
target-ppc/op_helper.c | 40 ++++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 42 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 88 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index f97480e..1dd2cf8 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -211,6 +211,12 @@ DEF_HELPER_4(vmsumuhs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumshm, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumshs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
+DEF_HELPER_2(lvebx, void, avr, tl)
+DEF_HELPER_2(lvehx, void, avr, tl)
+DEF_HELPER_2(lvewx, void, avr, tl)
+DEF_HELPER_2(stvebx, void, avr, tl)
+DEF_HELPER_2(stvehx, void, avr, tl)
+DEF_HELPER_2(stvewx, void, avr, tl)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index e6e6cb9..0c7473c 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2060,6 +2060,26 @@ SATCVT(sw, uh, int32_t, uint16_t, 0, UINT16_MAX, 1, 1)
SATCVT(sd, uw, int64_t, uint32_t, 0, UINT32_MAX, 1, 1)
#undef SATCVT
+#define LVE(name, access, swap, element) \
+ void helper_##name (ppc_avr_t *r, target_ulong addr) \
+ { \
+ size_t n_elems = N_ELEMS(element); \
+ int adjust = HI_IDX*(n_elems-1); \
+ int sh = sizeof(r->element[0]) >> 1; \
+ int index = (addr & 0xf) >> sh; \
+ if(msr_le) { \
+ r->element[LO_IDX ? index : (adjust - index)] =
swap(access(addr)); \
+ } else { \
+ r->element[LO_IDX ? index : (adjust - index)] = access(addr); \
+ } \
+ }
+#define I(x) (x)
+LVE(lvebx, ldub, I, u8)
+LVE(lvehx, lduw, bswap16, u16)
+LVE(lvewx, ldl, bswap32, u32)
+#undef I
+#undef LVE
+
void helper_lvsl (ppc_avr_t *r, target_ulong sh)
{
int i, j = (sh & 0xf);
@@ -2078,6 +2098,26 @@ void helper_lvsr (ppc_avr_t *r, target_ulong sh)
}
}
+#define STVE(name, access, swap, element) \
+ void helper_##name (ppc_avr_t *r, target_ulong addr) \
+ { \
+ size_t n_elems = N_ELEMS(element); \
+ int adjust = HI_IDX*(n_elems-1); \
+ int sh = sizeof(r->element[0]) >> 1; \
+ int index = (addr & 0xf) >> sh; \
+ if(msr_le) { \
+ access(addr, swap(r->element[LO_IDX ? index : (adjust - index)]));
\
+ } else { \
+ access(addr, r->element[LO_IDX ? index : (adjust - index)]); \
+ } \
+ }
+#define I(x) (x)
+STVE(stvebx, stb, I, u8)
+STVE(stvehx, stw, bswap16, u16)
+STVE(stvewx, stl, bswap32, u32)
+#undef I
+#undef LVE
+
void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
VECTOR_FOR(u32) {
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 985af3f..c7342a5 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6118,14 +6118,56 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001,
PPC_ALTIVEC) \
tcg_temp_free(EA); \
}
+#define GEN_VR_LVE(name, opc2, opc3) \
+ GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
+ { \
+ TCGv EA, rs; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ rs = gen_avr_ptr(rS(ctx->opcode)); \
+ gen_helper_lve##name (rs, EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free(rs); \
+ }
+
+#define GEN_VR_STVE(name, opc2, opc3) \
+ GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
+ { \
+ TCGv EA, rs; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ rs = gen_avr_ptr(rS(ctx->opcode)); \
+ gen_helper_stve##name (rs, EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free(rs); \
+ }
+
GEN_VR_LDX(lvx, 0x07, 0x03);
/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
GEN_VR_LDX(lvxl, 0x07, 0x0B);
+GEN_VR_LVE(bx, 0x07, 0x00);
+GEN_VR_LVE(hx, 0x07, 0x01);
+GEN_VR_LVE(wx, 0x07, 0x02);
+
GEN_VR_STX(svx, 0x07, 0x07);
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
GEN_VR_STX(svxl, 0x07, 0x0F);
+GEN_VR_STVE(bx, 0x07, 0x04);
+GEN_VR_STVE(hx, 0x07, 0x05);
+GEN_VR_STVE(wx, 0x07, 0x06);
+
GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
{
TCGv_ptr rd;
--
1.6.0.5
- [Qemu-devel] [PATCH 22/42] target-ppc: add vs{l,r} instructions., (continued)
- [Qemu-devel] [PATCH 22/42] target-ppc: add vs{l,r} instructions., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 27/42] target-ppc: add vsplt{b, h, w} instructions., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 32/42] target-ppc: add vmsum{u, m}bm instructions., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 37/42] target-ppc: add vmh{, r}addshs instructions., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 33/42] target-ppc: add vsel and vperm instructions., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 05/42] target-ppc: add v{add, sub}u{b, h, w}m instructions., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 11/42] target-ppc: add vscr access macros., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 16/42] target-ppc: add vs{l,r}o instructions., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 20/42] target-ppc: add v{add, sub}{s, u}{b, h, w}s instructions., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 38/42] target-ppc: add vmsumuh{m, s} instructions., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 41/42] target-ppc: add {l, st}ve{b, h, w}x instructions.,
Nathan Froyd <=
- [Qemu-devel] [PATCH 24/42] target-ppc: add GEN_VXFORM_SIMM macro for subsequent instructions., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 40/42] target-ppc: add vmladduhm instruction., Nathan Froyd, 2008/12/14
- [Qemu-devel] [PATCH 25/42] target-ppc: add vspltis{b, h, w} instructions., Nathan Froyd, 2008/12/15
- Re: [Qemu-devel] [PATCH] target-ppc: add Altivec instructions, patch-bomb version, Aurelien Jarno, 2008/12/15