[Qemu-devel] SH: Improve the interrupt controller

[Vladimir Prus]

This patch improves the intc implementation in these ways:

   - On interrupt, the priority mask in SSR is updated,
     if OPM register tells it should be
   - We check interrupt priority and compare it with
     priority mask
   - Priorities for IRL interrupts (which are fixed), are
     assigned
   - The ICR register is supported, and LVLMODE bit, which
     controls if interrupt is automatically de-asserted,
     is implemented
   - A bug where handling of paired set mask / clear mask
     registers was done backward is fixed
   - A bug where enabling a group did not work was fixed.

I have tested this only with SH4A and it's desirable to test
with 7751/R2D. However, I no longer sure I know which kernel
to use for that. Can anybody either provide me with instructions,
or test this patch with R2D for me?

- Volodya

intc.diff
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