Re: [Qemu-devel] [PATCH] target-ppc: initialize MSR appropriately in user-mode

[Aurelien Jarno]

On Mon, Dec 08, 2008 at 11:13:51AM -0800, Nathan Froyd wrote:
> We shouldn't blindly initialize the floating-point bit in MSR; we should
> only do so if the processor we're targetting supports floating-point.
> We should also do the same thing with the Altivec and e500 bits.
> 
> Signed-off-by: Nathan Froyd <address@hidden>

I have fixed the problem by applying two different patches, one to mask
the computed MSR with the MSR mask, and one to active Altivec and SPE.

Thanks for you work.

> diff --git a/target-ppc/helper.c b/target-ppc/helper.c
> index 6bffa06..1a4d69e 100644
> --- a/target-ppc/helper.c
> +++ b/target-ppc/helper.c
> @@ -2905,7 +2905,13 @@ void cpu_ppc_reset (void *opaque)
>      msr |= (target_ulong)1 << MSR_BE;
>  #endif
>  #if defined(CONFIG_USER_ONLY)
> -    msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
> +    /* Initialize MSR with appropriate instruction capabilities.  */
> +    if (env->msr_mask & ((target_ulong)1 << MSR_FP))
> +      msr |= (target_ulong)1 << MSR_FP;
> +    if (env->msr_mask & ((target_ulong)1 << MSR_VR))
> +      msr |= (target_ulong)1 << MSR_VR;
> +    if (env->msr_mask & ((target_ulong)1 << MSR_SPE))
> +      msr |= (target_ulong)1 << MSR_SPE;
>      msr |= (target_ulong)1 << MSR_PR;
>  #else
>      env->nip = env->hreset_vector | env->excp_prefix;
> 
> 
> 
> 

-- 
  .''`.  Aurelien Jarno             | GPG: 1024D/F1BCDB73
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