[Qemu-devel] can anybody check ?

[William PECNIK]

Hello, 
Perhaps not the good way to report a "potential" bug, but i try ....
in hw/fdc.c in qemu-0.9.1.tar.gz line 768-781

static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
{
    uint32_t retval = 0;

    /* Drive motors state indicators */
    if (drv0(fdctrl)->drflags & FDRIVE_MOTOR_ON)
        retval |= 1 << 5;  
    if (drv1(fdctrl)->drflags & FDRIVE_MOTOR_ON)
        retval |= 1 << 4;
    /* DMA enable */
    retval |= fdctrl->dma_en << 3;
    /* Reset indicator */
    retval |= (fdctrl->state & FD_CTRL_RESET) == 0 ? 0x04 : 0;
    /* Selected drive */
    retval |= fdctrl->cur_drv;
    FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);

    return retval;
}

In my book PC Programming System edition CampuPress they say:
bit 7 r/w motor on drive 3
bit 6 r/w motor on drive 2
bit 5 r/w motor on drive 1
bit 4 r/w motor on drive 0, 
... for the port 0x3F2
and as i can see in source it is inverse , can anybody confirm ?

thanks a lot 

william pecnik