Re: [Qemu-devel] [RFC] TCG new op: setcond

[Blue Swirl]

On 11/5/08, Laurent Desnogues <address@hidden> wrote:
> Hello,
>
>  Here is an updated patch for setcond.
>
>  Changes since the previous patch:
>
>   - support TCG i386 for 32 and 64 bit variants
>   - support TCG x86_64 support for 32 and 64 bit variants
>   - fix for x86_64 prefix output
>   - fix for input/output overlap
>   - use setcond for Alpha cmp instructions
>   - add setcondi
>
>  Digging into x86 is certainly not a pleasant experience for me,
>  especially as I have no experience on it.  So this patch may
>  contain bugs and overlooks;  note however my changes were
>  tested on x86_64 and i386 platforms with test programs for
>  Alpha and ARM.
>
>  What remains to be done:
>
>
>   - document setcond in tcg/README
>
>   - implement it in all backends (ARM, PPC, PPC64, SPARC)

There is no equivalent instruction for Sparc32 (V8), it should be
implemented otherwise. Though currently we assume that V9 is always
available.

Sparc64 (V9) has a conditional move instruction (MOVcc). The manual
suggests a three-instruction sequence (cmp, mov, movcc) to implement a
setcond-type operation. For setcondi where the immediate value is
zero, MOVR may be used to skip the comparison (mov, movrcc).

>  - use it at least once in every frontend (cris, i386, m68k, MIPS,
>    PPC, sh4, SPARC)

Candidate brconds to be replaced by setcond in target-sparc/translate
are: all of gen_cc_*, gen_op_mulscc, gen_op_div_cc and gen_cond_reg.
Especially gen_cond_reg should benefit.

> Also there's a choice to be done between return 1 if the test
> succeeds or -1.

'1' would be much more useful than '-1' for Sparc target, because it
can be shifted to form PSR_xxx values that can be or'ed to the
condition codes. All of the above candidates except gen_cond_reg would
need additional masking to remove the other bits than the zeroth.