[Qemu-devel] [PATCH 3/3] gdbstub: x86: Switch 64/32 bit registers dynamically

[Jan Kiszka]

Commit 5459 broke dynamic register set switching of gdbstub for x86-64.
This prevents setting the correct architecture in gdb when debugging 32
or 16-bit code in a 64-bit emulator. Reintroduces the feature over
previous refactorings.

Signed-off-by: Jan Kiszka <address@hidden>
---
 gdbstub.c         |   54 ++++++++++++++++++++++++++++++++++++++++++------------
 target-i386/cpu.h |    7 +++++--
 2 files changed, 47 insertions(+), 14 deletions(-)

Index: b/gdbstub.c
===================================================================
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -302,8 +302,9 @@ static const int gpr_map[16] = {
     8, 9, 10, 11, 12, 13, 14, 15
 };
 #else
-static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
+#define gpr_map gpr_map32
 #endif
+static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 
 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
 
@@ -317,9 +318,18 @@ static int cpu_gdb_read_register(CPUStat
 {
     switch (n) {
     case 0 ... CPU_NB_REGS - 1:
-        GET_REGL(env->regs[gpr_map[n]]);
+        if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK))
+            GET_REGL(env->regs[gpr_map[n]]);
+        else if (n < CPU_NB_REGS32)
+            GET_REG32(env->regs[gpr_map32[n]]);
+        else
+            return 0;
 
-    case IDX_IP_REG:   GET_REGL(env->eip);
+    case IDX_IP_REG:
+        if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK))
+            GET_REG64(env->eip);
+        else
+            GET_REG32(env->eip);
     case IDX_FLAG_REG: GET_REG32(env->eflags);
 
     case IDX_SEG_REGS + 0: GET_REG32(env->segs[R_CS].selector);
@@ -349,12 +359,17 @@ static int cpu_gdb_read_register(CPUStat
 
     case IDX_XMM_REGS ... IDX_XMM_REGS + CPU_NB_REGS:
         n -= IDX_XMM_REGS;
-        if (n < CPU_NB_REGS) {
+        if (n < CPU_NB_REGS32
+            || (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)
+                && n < CPU_NB_REGS64)) {
             stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
             stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
             return 16;
-        } else
+        } else if ((TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)
+                    && n == CPU_NB_REGS64) || n == CPU_NB_REGS32) {
             GET_REG32(env->mxcsr);
+        } else
+            return 0;
 
     default: /* Unrecognised register */
         return 0;
@@ -404,12 +419,23 @@ static int cpu_gdb_write_register(CPUSta
 
     switch (n) {
     case 0 ... CPU_NB_REGS - 1:
-        env->regs[gpr_map[n]] = ldtul_p(mem_buf);
-        return sizeof(target_ulong);
+        if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)) {
+            env->regs[gpr_map[n]] = ldtul_p(mem_buf);
+            return sizeof(target_ulong);
+        } else if (n < CPU_NB_REGS32) {
+            env->regs[gpr_map32[n]] = ldl_p(mem_buf);
+            return 4;
+        } else
+            return 0;
 
     case IDX_IP_REG:
-        env->eip = ldtul_p(mem_buf);
-        return sizeof(target_ulong);
+        if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)) {
+            env->eip = ldq_p(mem_buf);
+            return 8;
+        } else {
+            env->eip = ldl_p(mem_buf);
+            return 4;
+        }
     case IDX_FLAG_REG:
         env->eflags = ldl_p(mem_buf);
         return 4;
@@ -445,14 +471,18 @@ static int cpu_gdb_write_register(CPUSta
 
     case IDX_XMM_REGS ... IDX_XMM_REGS + CPU_NB_REGS:
         n -= IDX_XMM_REGS;
-        if (n < CPU_NB_REGS) {
+        if (n < CPU_NB_REGS32
+            || (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)
+                && n < CPU_NB_REGS64)) {
             env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
             env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
             return 16;
-        } else {
+        } else if ((TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)
+                    && n == CPU_NB_REGS64) || n == CPU_NB_REGS32) {
             env->mxcsr = ldl_p(mem_buf);
             return 4;
-        }
+        } else
+            return 0;
 
     default: /* Unrecognised register */
         return 0;
Index: b/target-i386/cpu.h
===================================================================
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -501,10 +501,13 @@ typedef union {
 #endif
 #define MMX_Q(n) q
 
+#define CPU_NB_REGS64 16
+#define CPU_NB_REGS32 8
+
 #ifdef TARGET_X86_64
-#define CPU_NB_REGS 16
+#define CPU_NB_REGS CPU_NB_REGS64
 #else
-#define CPU_NB_REGS 8
+#define CPU_NB_REGS CPU_NB_REGS32
 #endif
 
 #define NB_MMU_MODES 2