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[Qemu-devel] [5588] target-ppc: fix XER accesses on 64-bit targets
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [5588] target-ppc: fix XER accesses on 64-bit targets |
Date: |
Sat, 01 Nov 2008 00:53:48 +0000 |
Revision: 5588
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5588
Author: aurel32
Date: 2008-11-01 00:53:48 +0000 (Sat, 01 Nov 2008)
Log Message:
-----------
target-ppc: fix XER accesses on 64-bit targets
Signed-off-by: Aurelien Jarno <address@hidden>
Modified Paths:
--------------
trunk/target-ppc/translate.c
Modified: trunk/target-ppc/translate.c
===================================================================
--- trunk/target-ppc/translate.c 2008-11-01 00:53:39 UTC (rev 5587)
+++ trunk/target-ppc/translate.c 2008-11-01 00:53:48 UTC (rev 5588)
@@ -707,7 +707,8 @@
{
int l1, l2, l3;
- tcg_gen_shri_i32(cpu_crf[crf], cpu_xer, XER_SO);
+ tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
+ tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
l1 = gen_new_label();
@@ -1821,17 +1822,17 @@
tcg_gen_brcondi_tl(TCG_COND_GE, temp, 0, l1);
tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
- tcg_gen_ori_i32(cpu_xer, cpu_xer, 1 << XER_CA);
+ tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
+ tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
gen_set_label(l2);
tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], temp, sh);
tcg_temp_free(temp);
} else {
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
- tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
+ tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
}
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
@@ -1901,15 +1902,15 @@
temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
- tcg_gen_ori_i32(cpu_xer, cpu_xer, 1 << XER_CA);
+ tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
+ tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
gen_set_label(l2);
tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
sh);
} else {
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
- tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
+ tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
}
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
@@ -3637,7 +3638,7 @@
{
tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],
XER_CA);
- tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 <<
XER_CA));
+ tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 <<
XER_CA));
}
/* mfcr */
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