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[Qemu-devel] [4858] Implement some Ultrasparc cache ASIs used by SILO
From: |
Blue Swirl |
Subject: |
[Qemu-devel] [4858] Implement some Ultrasparc cache ASIs used by SILO |
Date: |
Tue, 08 Jul 2008 15:51:33 +0000 |
Revision: 4858
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4858
Author: blueswir1
Date: 2008-07-08 15:51:32 +0000 (Tue, 08 Jul 2008)
Log Message:
-----------
Implement some Ultrasparc cache ASIs used by SILO
Modified Paths:
--------------
trunk/target-sparc/op_helper.c
Modified: trunk/target-sparc/op_helper.c
===================================================================
--- trunk/target-sparc/op_helper.c 2008-07-07 23:01:25 UTC (rev 4857)
+++ trunk/target-sparc/op_helper.c 2008-07-08 15:51:32 UTC (rev 4858)
@@ -1687,6 +1687,16 @@
}
break;
}
+ case 0x46: // D-cache data
+ case 0x47: // D-cache tag access
+ case 0x4e: // E-cache tag data
+ case 0x66: // I-cache instruction access
+ case 0x67: // I-cache tag access
+ case 0x6e: // I-cache predecode
+ case 0x6f: // I-cache LRU etc.
+ case 0x76: // E-cache tag
+ case 0x7e: // E-cache tag
+ break;
case 0x59: // D-MMU 8k TSB pointer
case 0x5a: // D-MMU 64k TSB pointer
case 0x5b: // D-MMU data pointer
@@ -2040,6 +2050,16 @@
case 0x49: // Interrupt data receive
// XXX
return;
+ case 0x46: // D-cache data
+ case 0x47: // D-cache tag access
+ case 0x4e: // E-cache tag data
+ case 0x66: // I-cache instruction access
+ case 0x67: // I-cache tag access
+ case 0x6e: // I-cache predecode
+ case 0x6f: // I-cache LRU etc.
+ case 0x76: // E-cache tag
+ case 0x7e: // E-cache tag
+ return;
case 0x51: // I-MMU 8k TSB pointer, RO
case 0x52: // I-MMU 64k TSB pointer, RO
case 0x56: // I-MMU tag read, RO
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