Re: [Qemu-devel] [PATCH] Asynchronous reliable and configurable cache flush

[Ian Jackson]

Samuel Thibault writes ("Re: [Qemu-devel] [PATCH] Asynchronous reliable and 
configurable cache flush"):
> Oh, by the way, shouldn't this:
> Ian Jackson, le Tue 01 Apr 2008 18:18:59 +0100, a écrit :
> >      put_le16(p + 81, 0x16); /* conforms to ata5 */
> > -    put_le16(p + 82, (1 << 14));
> > +    /* 14=nop 5=write_cache */
> > +    put_le16(p + 82, (1 << 14) | (1 << 5));
> >      /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
> 
> use s->write_cache instead of always 1?  Else when using hdparm -i one
> would think that write cache is always enabled.

No.  According to the ATA-7 draft I have in front of me, the meaning
of word 82 is `Command set supported' and the meaning of bit 5 is is
`write cache supported'.

Word 85 bit 5 is `write cache enabled'.  I see that the patch I
supplied earlier is missing this, which I will fix.

Ian.