Re: [Qemu-devel] sparc32 counter/timer issues

[Blue Swirl]

On 9/21/07, Robert Reif <address@hidden> wrote:
> I'm trying to run a real ss10 openboot prom image rather than
> the supplied prom image and found some issues with the way
> counters and timers are implemented.  It appears that the processor
> and system counter/timers are not independent.  The system
> config register actually configures the processor counter/timers
> and the config register is actually a bit mask of the counter/timer
> to configure. 1, 2, 4, and 8 are used to as config values for each
> processor counter/timer and 0xf is used for setting all of them.
> This isn't apparent in the slaveio documentation because it is
> for a single cpu only.
>
> Because the system config register configures the processor
> timers, it needs access to all the processor timers (or the
> processor timers need access to the system timer).  This isn't
> how it's currently implemented.

Thanks for testing. This patch changes the config register to what you
described, everything seems to work like before. Do you see any
difference?

timer_fix.diff
Description: Text Data