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Re: [Qemu-devel] Re: PATCH, RFC: Generic DMA framework

From: Blue Swirl
Subject: Re: [Qemu-devel] Re: PATCH, RFC: Generic DMA framework
Date: Wed, 29 Aug 2007 20:00:43 +0300

On 8/28/07, Paul Brook <address@hidden> wrote:
> > On second thought, there is a huge difference between a write access
> > originating from CPU destined for the device and the device writing to
> > main memory. The CPU address could be 0xf000 1000, which may translate
> > to a bus address of 0x1000, as an example. The device could write to
> > main memory using the same bus address 0x1000, but this time the IOMMU
> > would map this to for example 0x1234 5000, or without an IOMMU it
> > would be just 0x1000.
> While your concern is valid, your example is not.
> You can't have the same bus address mapping onto both a device and main
> memory. Your example works if e.g. IO bus address 0x2000 1000 (or worse still
> 0xf000 1000) maps onto system memory 0x1234 5000.

This is a bit mysterious for me too. SBus address space is 28 bits
(256MB). Usually each slot maps to a different area. So the CPU sees
one slot for example at 0x3000 0000 and other at 0x4000 0000.

IOMMU can map max 2G of memory, usually a 32 or 64MB region. For the
devices, this device virtual memory access (DVMA) space exists at the
top of address space (for example 0xfc00 0000). Each page can map to a
different address. But these mappings can not be seen from CPU, for
example the boot prom is located at 0xffd0 0000. I wonder how the
devices access the DVMA space in case of >256M DVMA.

The device can't obviously supply the address bits 28-31, I don't know
where they come from (=1?). But from tracing Linux I'm pretty sure
that the bus address can be 0 disregarding the higher bits and also
the device (or device FCode prom more likely) can exist at that
location. How? Maybe IOMMU does not see CPU accesses at all and the
devices see neither each other nor themselves, so it's not a really a
shared bus?

> Conceptually you can have a separate IOMMU on every bus-bus or bus/host
> bridge, with asymmetric mappings depending where the transaction originates.

IOMMU on Sun4m maps DVMA addresses to physical addresses, which (I
think) in turn can be other device's registers or memory, but the
mappings are same for all devices.

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