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RE: [Qemu-devel] sparc system emulator scsi write delays

From: Blue Swirl
Subject: RE: [Qemu-devel] sparc system emulator scsi write delays
Date: Tue, 14 Feb 2006 20:34:12 +0100

I'm trying to get the sparc system emulator going... I'm booting it

Good, new developers are most welcome!

After experimenting with some writes using dd, I noticed that blocks
were only getting to the disk image after a 1 write delay.  With some
observation of the ESP debug trace, I
figured out that writes are happening ahead of the DMA transfers of
the data from the blocks to be written... So a write actually writes
whatever was hanging around in the buffer from the last DMA transfer,
and then reloads the buffer afterward.  You can see in the
ESP debug trace below where the write happens ('Write (10)') and the
DMA transfer below
it ('Transfer Information len 512').

Thanks for the report, your analysis is correct. Looking at the dump, the logic of writing is indeed wrong. The write operation really should start only after DMA has finished.

I hadn't tested writing at all so far, only reading. Now I wonder if all transfers in CPU->ESP direction have the same bug...

that I'm not seeing. Can someone point me at detailed specs online

I'm using these as well as Linux sources:

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