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[Qemu-devel] Re: PowerPC power management


From: Peter Grayson
Subject: [Qemu-devel] Re: PowerPC power management
Date: Wed, 06 Apr 2005 17:40:18 -0600

On Thu, 2005-04-07 at 00:26 +0200, J. Mayer wrote:
> PPC power management is much more complicated than what you've done. I
> already have a patch for this but, in some cases, the OS fails to go out
> of power management. Most Linux version does, a few freeze. That's why
> the patch has never been commited until now.
> 
> Then, your patch is buggy: there are _really_ three pm modes for PPC
> cpus, so masking the mode with 1 is not correct. And it seems to me that
> there are checks missing to know when normal execution is to be resumed:
> some PM modes should disable IRQs, some should disable timers, ....
> Another point is that not all PPCs use those bits for PM and the way
> those bits are interpreted change between PPC versions.
> 

I appreciate you looking at this patch. In reference to the POW bit(s),
I did not realize that there was more than one POW bit. I was
referencing PPC 405, 604, 740/750, and 970 documentation. For the 604,
740, 750, and 970 there is just one POW bit; in the 405 they call the
bit WE (wait state enable), but it is in the same position in the MSR
and has the same semantics as the POW bit. I did see that 740, 750, and
970s have some extra bits in the HID0 register (e.g. NAP) that provide
extended power management semantics. I chose to totally ignore that
complication.

Obviously what I did was a gross approximation, at the functional level,
of what the POW bit should do. It do not believe it has the problem of
not knowing when to resume normal execution. All that happens at the end
of cpu_exec(), if the POW bit was left asserted, main_loop() waits 10
milliseconds instead of 0 milliseconds before executing the next
instruction. This means that qemu is never hung-up indefinitely.
Furthermore, there are several conditions that cause the POW bit to be
deasserted, most notably every interrupt resets this bit. I believe that
the kernel has to continuously be asserting the POW bit to maintain the
quasi-low-power state.

I am certainly not pushing to get this patch applied to qemu -- it is a
hack. I am glad to hear you are working on a real solution to this
problem -- more power to you!

Pete




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