Index: linux-user/main.c
===================================================================
RCS file: /cvsroot/qemu/qemu/linux-user/main.c,v
retrieving revision 1.61
diff -u -r1.61 main.c
--- linux-user/main.c	19 Feb 2005 17:25:31 -0000	1.61
+++ linux-user/main.c	2 Mar 2005 12:37:49 -0000
@@ -325,18 +325,45 @@
             {
                 TaskState *ts = env->opaque;
                 uint32_t opcode;
+                int rc;
 
                 /* we handle the FPU emulation here, as Linux */
                 /* we get the opcode */
                 opcode = ldl_raw((uint8_t *)env->regs[15]);
                 
-                if (EmulateAll(opcode, &ts->fpa, env->regs) == 0) {
+                if ((rc=EmulateAll(opcode, &ts->fpa, env->regs)) == 0) { /* illegal instruction */
                     info.si_signo = SIGILL;
                     info.si_errno = 0;
                     info.si_code = TARGET_ILL_ILLOPN;
                     info._sifields._sigfault._addr = env->regs[15];
                     queue_signal(info.si_signo, &info);
-                } else {
+                } else if (rc < 0) { /* FP exception */
+                    FPSR fpsr = ts->fpa.fpsr;
+                    //printf("fpsr 0x%x, -rc 0x%x\n",fpsr,-rc);
+                    if(fpsr & (-rc << 16))	/* exception enabled? */
+                    {
+                      info.si_signo = SIGFPE;
+                      info.si_errno = 0;
+                      /* ordered by priority, least first */
+                      if(-rc & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
+                      if(-rc & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
+                      if(-rc & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
+                      if(-rc & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
+                      if(-rc & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
+                      info._sifields._sigfault._addr = env->regs[15];
+                      queue_signal(info.si_signo, &info);
+                    }
+                    else
+                      env->regs[15] += 4;
+                    
+                    /* accumulate unenabled exceptions */
+                    if((!(fpsr & BIT_IXE)) && (-rc & BIT_IXC)) fpsr |= BIT_IXC;
+                    if((!(fpsr & BIT_UFE)) && (-rc & BIT_UFC)) fpsr |= BIT_UFC;
+                    if((!(fpsr & BIT_OFE)) && (-rc & BIT_OFC)) fpsr |= BIT_OFC;
+                    if((!(fpsr & BIT_DZE)) && (-rc & BIT_DZC)) fpsr |= BIT_DZC;
+                    if((!(fpsr & BIT_IOE)) && (-rc & BIT_IOC)) fpsr |= BIT_IOC;
+                    ts->fpa.fpsr=fpsr;
+                } else { /* everything OK */
                     /* increment PC */
                     env->regs[15] += 4;
                 }
Index: target-arm/nwfpe/fpa11.c
===================================================================
RCS file: /cvsroot/qemu/qemu/target-arm/nwfpe/fpa11.c,v
retrieving revision 1.1
diff -u -r1.1 fpa11.c
--- target-arm/nwfpe/fpa11.c	16 Feb 2004 21:43:58 -0000	1.1
+++ target-arm/nwfpe/fpa11.c	2 Mar 2005 12:37:50 -0000
@@ -155,6 +155,8 @@
     SetRoundingPrecision(ROUND_EXTENDED);
     fpa11->initflag = 1;
   }
+  
+  float_exception_flags = 0;
 
   if (TEST_OPCODE(opcode,MASK_CPRT))
   {
@@ -185,6 +187,11 @@
   }
 
 //  restore_flags(flags);
+  if(nRc == 1 && float_exception_flags)
+  {
+    //printf("fef 0x%x\n",float_exception_flags);
+    nRc=-float_exception_flags;
+  }
 
   //printf("returning %d\n",nRc);
   return(nRc);