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From: | Fabrice Bellard |
Subject: | Re: [Qemu-devel] [PATCH] minor x86-64 corrections |
Date: | Fri, 21 Jan 2005 22:44:50 +0100 |
User-agent: | Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.7.3) Gecko/20040913 |
Filip Navara wrote:
Changelog: 2005-01-21 Filip Navara <address@hidden> * Add support for CR8 register. * Don't throw exception when assigning zero to SS register in 64-bit mode.BTW, the callgate support for x86-64 in long mode is broken. See "AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions", page 90. Anybody cares to fix it?
No time yet. It would be interesting to find the problem for the Linux user code too.
--- target-i386/helper.c 16 Jan 2005 23:35:43 -0000 1.40 +++ target-i386/helper.c 21 Jan 2005 20:13:30 -0000 @@ -1454,8 +1454,13 @@ selector &= 0xffff; if ((selector & 0xfffc) == 0) { /* null selector case */ - if (seg_reg == R_SS) + if (seg_reg == R_SS) { +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) + return; +#endif raise_exception_err(EXCP0D_GPF, 0); + } cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
Maybe the SS segment cache should be set to zero ?
+void OPPROTO op_movtl_T0_cr7(void) +{ + T0 = (cpu_get_apic_tpr(env) & 0xf) >> 4; +}
Why do you call it cr7 ? Fabrice.
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