Re: [Qemu-devel] enabling bus-master IDE driver

[Juergen Lock]

On Sat, Nov 13, 2004 at 01:43:35AM +0000, Juergen Keil wrote:
> 
> 
> > > +    put_le16(p + 63, 0x07 /*| 0x4 << 8*/); /* Multiword DMA 
> supported/selected */
> ...
> > > +    put_le16(p + 88, 0x3f | 0x20 << 8); /* UltraDMA modes 
> supported/selected */
> 
> > This is interesting..
> > 
> > I carefully applied these changes to my ide.c and retried:
> > 
> > Host: Linux 2.6 (Fedora Core 2)
> > Guest: XP corp.
> > It now says "Current Transfer Mode: Multi-Word DMA Mode 2".
> > I'm not real sure how I test to see if disk access is faster,
> > or by how much, but this appears to be progress for XP.
> 
> Windows 2000 isn't that verbose - it simply prints "DMA mode".
> 
> Interesting that XP has enabled "Multi-Word DMA Mode 2".
>...

FreeBSD guests (at least 5.3-BETA1) say they use WDMA2, which i guess
is the same:

Copyright (c) 1992-2004 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
        The Regents of the University of California. All rights reserved.
FreeBSD 5.3-BETA1 #0: Sat Aug 21 08:19:34 UTC 2004
    address@hidden:/usr/obj/usr/src/sys/GENERIC
...
atapci0: <Intel PIIX3 WDMA2 controller> port 
0xc000-0xc00f,0x376,0x170-0x177,0x3f6,0x1f0-0x1f7 at device 1.1 on pci0
atapci0: Reserved 0x10 bytes for rid 0x20 type 4 at 0xc000
ata0: channel #0 on atapci0
atapci0: Reserved 0x8 bytes for rid 0x10 type 4 at 0x1f0
atapci0: Reserved 0x1 bytes for rid 0x14 type 4 at 0x3f6
ata0: reset tp1 mask=03 ostat0=50 ostat1=00
ata0-master: stat=0x50 err=0x01 lsb=0x00 msb=0x00
ata0-slave:  stat=0x00 err=0x01 lsb=0xff msb=0xff
ata0: reset tp2 stat0=50 stat1=00 devices=0x1<ATA_MASTER>
ata0: [MPSAFE]
ata1: channel #1 on atapci0
atapci0: Reserved 0x8 bytes for rid 0x18 type 4 at 0x170
atapci0: Reserved 0x1 bytes for rid 0x1c type 4 at 0x376
ata1: reset tp1 mask=03 ostat0=00 ostat1=00
ata1-master: stat=0x00 err=0x01 lsb=0x14 msb=0xeb
ata1-slave:  stat=0x00 err=0x01 lsb=0xff msb=0xff
ata1: reset tp2 stat0=00 stat1=00 devices=0x4<ATAPI_MASTER>
ata1: [MPSAFE]
...
ata0-master: pio=0x0c wdma=0x22 udma=0x45 cable=80pin
ata0-master: setting PIO4 on Intel PIIX3 chip
ata0-master: setting WDMA2 on Intel PIIX3 chip
ad0: <QEMU HARDDISK/0.6.1> ATA-2 disk at ata0-master
ad0: 488MB (1000000 sectors), 992 C, 16 H, 63 S, 512 B
ad0: 16 secs/int, 1 depth queue, WDMA2
...
ata1-master: pio=0x0c wdma=0x22 udma=0x45 cable=40pin
ATAPI_RESET time = 0us
ata1-master: setting PIO4 on Intel PIIX3 chip
ata1-master: setting WDMA2 on Intel PIIX3 chip
acd0: <QEMU CD-ROM/0.6.1> CDROM drive at ata1 as master
acd0: read 689KB/s (689KB/s), 512KB buffer, WDMA2
acd0: Reads:
acd0: Writes:
acd0: Mechanism: ejectable tray, unlocked
acd0: Medium: no/blank disc
...

 Here is a version of the patch that applies to 0.6.1 and cvs (up to now)
so others can test it more easily (with dma for cdrom), tell me if i
applied something wrong:

Index: qemu/hw/ide.c
@@ -430,6 +430,8 @@
         put_le16(p + 59, 0x100 | s->mult_sectors);
     put_le16(p + 60, s->nb_sectors);
     put_le16(p + 61, s->nb_sectors >> 16);
+    put_le16(p + 63, 0x07 /*| 0x4 << 8*/); /* Multiword DMA supported/selected 
*/
+    put_le16(p + 64, 0x3f); /* PIO modes supported */
     put_le16(p + 80, (1 << 1) | (1 << 2));
     put_le16(p + 82, (1 << 14));
     put_le16(p + 83, (1 << 14));
@@ -437,7 +439,7 @@
     put_le16(p + 85, (1 << 14));
     put_le16(p + 86, 0);
     put_le16(p + 87, (1 << 14));
-    put_le16(p + 88, 0x1f | (1 << 13));
+    put_le16(p + 88, 0x3f | (1 << 13)); /* UltraDMA modes supported/selected */
     put_le16(p + 93, 1 | (1 << 14) | 0x2000 | 0x4000);
 }
 
@@ -458,10 +460,10 @@
     padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
     padstr((uint8_t *)(p + 27), "QEMU CD-ROM", 40); /* model */
     put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
-    put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
-    put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
-    put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
-    put_le16(p + 64, 1); /* PIO modes */
+    put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
+    put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
+    put_le16(p + 63, 7 /*| 0x4 << 8*/); /* Multiword DMA supported/selected */
+    put_le16(p + 64, 0x3f); /* PIO modes supported */
     put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
     put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
     put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
@@ -471,6 +473,7 @@
     put_le16(p + 72, 30); /* in ns */
 
     put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
+    put_le16(p + 88, 0x3f | 0x20 << 8); /* UltraDMA modes supported/selected */
 }
 
 static void ide_set_signature(IDEState *s)
@@ -500,6 +503,10 @@
 static inline void ide_set_irq(IDEState *s)
 {
     if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
+       BMDMAState *bm = s->bmdma;
+       if(bm)
+           bm->status |= BM_STATUS_INT;
+
 #ifdef TARGET_PPC
         if (s->openpic) 
             openpic_set_irq(s->openpic, s->irq, 1);
@@ -2176,6 +2183,7 @@
     pci_conf[0x01] = 0x80;
     pci_conf[0x02] = 0x10;
     pci_conf[0x03] = 0x70;
+    pci_conf[0x09] = 0x8a; // programming interface = PCI_IDE bus master is 
supported
     pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
     pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
     pci_conf[0x0e] = 0x00; // header_type