Re: [Qemu-devel] qemu and solaris, suggested pci-ide DMA PATCH

[Juergen Keil]

I wrote:

> As far as I understand it, the Solaris ata driver does not use DMA
> transfers with the "pci-ide" qemu hardware, because the "bus master
> support indicator" bit in pci configuration space offset 09h is not
> set.
> 
> The message from the Solaris 10 b63 kernel is something like:
> 
>   "ATA DMA off: cntrl not Bus Master DMA capable"
> 
> So it'll fall back to PIO mode transfers.  PIO transfers may be slow, but
> that's OK, so far.

The following patch changes the qemu pci-ide device to report a
"pci buster master ide controller" instead of a "pci ide controller
(without bus master support)".  With that patch installed, a Solaris x86
guest os starts using DMA ide transfers.  Maximum transfer rates on the qemu
ide hdd doubles (I observe ~10MByte/sec in DMA mode vs. ~5MByte/sec in PIO
mode). 

(The patch includes the busmaster status register patch I send two days ago,
to enable the pci-ide controller for Solaris x86 in qemu "-pci" mode)


Index: hw/ide.c
===================================================================
RCS file: /cvsroot/qemu/qemu/hw/ide.c,v
retrieving revision 1.26
diff -u -B -u -6 -r1.26 ide.c
--- hw/ide.c    25 Jun 2004 14:54:19 -0000      1.26
+++ hw/ide.c    3 Sep 2004 12:45:14 -0000
@@ -495,12 +495,16 @@
     s->error = ABRT_ERR;
 }
 
 static inline void ide_set_irq(IDEState *s)
 {
     if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
+       BMDMAState *bm = s->bmdma;
+       if(bm)
+           bm->status |= BM_STATUS_INT;
+
 #ifdef TARGET_PPC
         if (s->openpic) 
             openpic_set_irq(s->openpic, s->irq, 1);
         else 
 #endif
         if (s->irq == 16)
@@ -2152,12 +2156,13 @@
                                            NULL, NULL);
     pci_conf = d->dev.config;
     pci_conf[0x00] = 0x86; // Intel
     pci_conf[0x01] = 0x80;
     pci_conf[0x02] = 0x10;
     pci_conf[0x03] = 0x70;
+    pci_conf[0x09] = 0x8a; // programming interface = PCI_IDE bus master is 
supported
     pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
     pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
     pci_conf[0x0e] = 0x00; // header_type
 
     pci_register_io_region((PCIDevice *)d, 4, 0x10, 
                            PCI_ADDRESS_SPACE_IO, bmdma_map);