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[Qemu-devel] register load/store optimization ideas...

From: Chad Page
Subject: [Qemu-devel] register load/store optimization ideas...
Date: Thu, 30 Oct 2003 11:32:47 -0800 (PST)

        I'm looking at the intermediate code more closely (I actually get
how byte/word regs are handled now) and I'm trying to figure out how to
get redundant register loads/stores out of there as efficently as

        I'm thinking the DEF for instructions could be ammended to include
a register alias field, so you could have things like:

        rT0_EAX - read from EAX - set alias, remove instruction if alias
already exists.

        sT0_EAX - store in EAX - set alias.

        modT0 - T0 is changed, break aliases.
        The aliases could then be used in an optimization pass which would
remove redundant loads and then stores.  This would be more beneficial for
user mode since the memory mapping stuff is taking most of the
instructions in softmmu mode right now. 

        There could be some operation-specific optimizations too, such as
the repeated movb/outb case, where the movl_T0_im should be loaded into T1
instead of T0, and then a bytewide load/store of eax can be removed.

        - Chad

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