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[Qemu-commits] [qemu/qemu] 0b9033: target/arm: Add Neoverse-N1 registers


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 0b9033: target/arm: Add Neoverse-N1 registers
Date: Tue, 21 Mar 2023 10:14:53 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0b903369951cac12ccdfc66a7520b413eca1bb62
      
https://github.com/qemu/qemu/commit/0b903369951cac12ccdfc66a7520b413eca1bb62
  Author: Chen Baozi <chenbaozi@phytium.com.cn>
  Date:   2023-03-21 (Tue, 21 Mar 2023)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Add Neoverse-N1 registers

Add implementation defined registers for neoverse-n1 which
would be accessed by TF-A. Since there is no DSU in Qemu,
CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-id: 20230313033936.585669-1-chenbaozi@phytium.com.cn
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0c88f93788d33795a4c14a0ca999607a6546f8b8
      
https://github.com/qemu/qemu/commit/0c88f93788d33795a4c14a0ca999607a6546f8b8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-03-21 (Tue, 21 Mar 2023)

  Changed paths:
    M hw/char/cadence_uart.c

  Log Message:
  -----------
  hw/char/cadence_uart: Fix guards on invalid BRGR/BDIV settings

The cadence UART attempts to avoid allowing the guest to set invalid
baud rate register values in the uart_write() function.  However it
does the "mask to the size of the register field" and "check for
invalid values" in the wrong order, which means that a malicious
guest can get a bogus value into the register by setting also some
high bits in the value, and cause QEMU to crash by division-by-zero.

Do the mask before the bounds check instead of afterwards.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1493
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Qiang Liu <cyruscyliu@gmail.com>
Message-id: 20230314170804.1196232-1-peter.maydell@linaro.org


  Commit: 05adc48e1d60ebef57ca78626fbfce895a15664d
      
https://github.com/qemu/qemu/commit/05adc48e1d60ebef57ca78626fbfce895a15664d
  Author: Viktor Prutyanov <viktor@daynix.com>
  Date:   2023-03-21 (Tue, 21 Mar 2023)

  Changed paths:
    M contrib/elf2dmp/addrspace.c
    M contrib/elf2dmp/main.c
    M contrib/elf2dmp/pe.h

  Log Message:
  -----------
  contrib/elf2dmp: fix code style

Originally elf2dmp were added with some code style issues,
especially in pe.h header, and some were introduced by
2d0fc797faaa73fbc1d30f5f9e90407bf3dd93f0. Fix them now.

Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
Reviewed-by: Annie Li <annie.li@oracle.com>
Message-id: 20230222211246.883679-2-viktor@daynix.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 06ac60b73e6abe1209d0ed1aca69d7f79f95b30b
      
https://github.com/qemu/qemu/commit/06ac60b73e6abe1209d0ed1aca69d7f79f95b30b
  Author: Viktor Prutyanov <viktor@daynix.com>
  Date:   2023-03-21 (Tue, 21 Mar 2023)

  Changed paths:
    M contrib/elf2dmp/main.c

  Log Message:
  -----------
  contrib/elf2dmp: move PE dir search to pe_get_data_dir_entry

Move out PE directory search functionality to be reused not only
for Debug Directory processing but for arbitrary PE directory.

Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
Reviewed-by: Annie Li <annie.li@oracle.com>
Message-id: 20230222211246.883679-3-viktor@daynix.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d399d6b179f07b9904de0e76d06c77a3d0a66b51
      
https://github.com/qemu/qemu/commit/d399d6b179f07b9904de0e76d06c77a3d0a66b51
  Author: Viktor Prutyanov <viktor@daynix.com>
  Date:   2023-03-21 (Tue, 21 Mar 2023)

  Changed paths:
    M contrib/elf2dmp/main.c
    M contrib/elf2dmp/pe.h

  Log Message:
  -----------
  contrib/elf2dmp: add PE name check and Windows Server 2022 support

Since its inception elf2dmp has checked MZ signatures within an
address space above IDT[0] interrupt vector and took first PE image
found as Windows Kernel.
But in Windows Server 2022 memory dump this address space range is
full of invalid PE fragments and the tool must check that PE image
is 'ntoskrnl.exe' actually.
So, introduce additional validation by checking image name from
Export Directory against 'ntoskrnl.exe'.

Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
Tested-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Reviewed-by: Annie Li <annie.li@oracle.com>
Message-id: 20230222211246.883679-4-viktor@daynix.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3202b2628b470a2e44f3cc7b9582c724fe654bd1
      
https://github.com/qemu/qemu/commit/3202b2628b470a2e44f3cc7b9582c724fe654bd1
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2023-03-21 (Tue, 21 Mar 2023)

  Changed paths:
    M hw/usb/imx-usb-phy.c

  Log Message:
  -----------
  hw/usb/imx: Fix out of bounds access in imx_usbphy_read()

The i.MX USB Phy driver does not check register ranges, resulting in out of
bounds accesses if an attempt is made to access non-existing PHY registers.
Add range check and conditionally report bad accesses to fix the problem.

While at it, also conditionally log attempted writes to non-existing or
read-only registers.

Reported-by: Qiang Liu <cyruscyliu@gmail.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Qiang Liu <cyruscyliu@gmail.com>
Message-id: 20230316234926.208874-1-linux@roeck-us.net
Link: https://gitlab.com/qemu-project/qemu/-/issues/1408
Fixes: 0701a5efa015 ("hw/usb: Add basic i.MX USB Phy support")
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d4e2cc9aa4f2c8c4782fd18aa25e76d26e98111c
      
https://github.com/qemu/qemu/commit/d4e2cc9aa4f2c8c4782fd18aa25e76d26e98111c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-03-21 (Tue, 21 Mar 2023)

  Changed paths:
    M docs/system/arm/cpu-features.rst

  Log Message:
  -----------
  docs/system/arm/cpu-features.rst: Fix formatting

The markup for the Arm CPU feature documentation is incorrect,
and results in the HTML not rendering correctly -- the first
line of each description is rendered in boldface as if it
were part of the option name.

Reformat to match the styling used in cpu-models-x86.rst.inc.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1479
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230316105808.1414003-1-peter.maydell@linaro.org
Reviewed-by: Cornelia Huck <cohuck@redhat.com>


  Commit: 5787d17a42f7af4bd117e5d6bfa54b1fdf93c255
      
https://github.com/qemu/qemu/commit/5787d17a42f7af4bd117e5d6bfa54b1fdf93c255
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-03-21 (Tue, 21 Mar 2023)

  Changed paths:
    M target/arm/gdbstub.c

  Log Message:
  -----------
  target/arm: Don't advertise aarch64-pauth.xml to gdb

Unfortunately a bug in older versions of gdb means that they will
crash if QEMU sends them the aarch64-pauth.xml.  This bug is fixed in
gdb commit 1ba3a3222039eb25, and there are plans to backport that to
affected gdb release branches, but since the bug affects gdb 9
through 12 it is very widely deployed (for instance by distros).

It is not currently clear what the best way to deal with this is; it
has been proposed to define a new XML feature name that old gdb will
ignore but newer gdb can handle.  Since QEMU's 8.0 release is
imminent and at least one of our CI runners is now falling over this,
disable the pauth XML for the moment.  We can follow up with a more
considered fix either in time for 8.0 or else for the 8.1 release.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8de6e6e12e623ea402274d4cf24de20ed7e40717
      
https://github.com/qemu/qemu/commit/8de6e6e12e623ea402274d4cf24de20ed7e40717
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-03-21 (Tue, 21 Mar 2023)

  Changed paths:
    M contrib/elf2dmp/addrspace.c
    M contrib/elf2dmp/main.c
    M contrib/elf2dmp/pe.h
    M docs/system/arm/cpu-features.rst
    M hw/char/cadence_uart.c
    M hw/usb/imx-usb-phy.c
    M target/arm/cpu64.c
    M target/arm/gdbstub.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20230321' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * contrib/elf2dmp: Support Windows Server 2022
 * hw/char/cadence_uart: Fix guards on invalid BRGR/BDIV settings
 * target/arm: Add Neoverse-N1 IMPDEF registers
 * hw/usb/imx: Fix out of bounds access in imx_usbphy_read()
 * docs/system/arm/cpu-features.rst: Fix formatting
 * target/arm: Don't advertise aarch64-pauth.xml to gdb

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# CV7QPcDOR87jY228DT4EzA==
# =D7pq
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 21 Mar 2023 13:20:04 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20230321' of 
https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Don't advertise aarch64-pauth.xml to gdb
  docs/system/arm/cpu-features.rst: Fix formatting
  hw/usb/imx: Fix out of bounds access in imx_usbphy_read()
  contrib/elf2dmp: add PE name check and Windows Server 2022 support
  contrib/elf2dmp: move PE dir search to pe_get_data_dir_entry
  contrib/elf2dmp: fix code style
  hw/char/cadence_uart: Fix guards on invalid BRGR/BDIV settings
  target/arm: Add Neoverse-N1 registers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/42d55ab17069...8de6e6e12e62



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