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[Qemu-commits] [qemu/qemu] 9fd86b: tcg: Avoid recursion in tcg_gen_mulu2
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] 9fd86b: tcg: Avoid recursion in tcg_gen_mulu2_i32 |
Date: |
Fri, 03 Feb 2023 01:36:18 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 9fd86b518ee0abc0f0c013ce51e5384b8109d94c
https://github.com/qemu/qemu/commit/9fd86b518ee0abc0f0c013ce51e5384b8109d94c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Avoid recursion in tcg_gen_mulu2_i32
We have a test for one of TCG_TARGET_HAS_mulu2_i32 or
TCG_TARGET_HAS_muluh_i32 being defined, but the test
became non-functional when we changed to always define
all of these macros.
Replace this with a build-time test in tcg_gen_mulu2_i32.
Fixes: 25c4d9cc845 ("tcg: Always define all of the TCGOpcode enum members.")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1435
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1b18d1fa05bbf8d28778b0eb65dc21d4cd7c6950
https://github.com/qemu/qemu/commit/1b18d1fa05bbf8d28778b0eb65dc21d4cd7c6950
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target-con-str.h
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Use register pair allocation for qemu_{ld,st}_i64
Although we still can't use ldrd and strd for all operations,
increase the chances by getting the register allocation correct.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ffe98631b36ebb39a0478501e271e11a5feeb15f
https://github.com/qemu/qemu/commit/ffe98631b36ebb39a0478501e271e11a5feeb15f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
A common-user/host/ppc/safe-syscall.inc.S
Log Message:
-----------
common-user/host/ppc: Implement safe-syscall.inc.S
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220729172141.1789105-2-richard.henderson@linaro.org>
Commit: 2466bb3b083f965ef1ec12368c07e7d1e2f0b4c4
https://github.com/qemu/qemu/commit/2466bb3b083f965ef1ec12368c07e7d1e2f0b4c4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
A linux-user/include/host/ppc/host-signal.h
Log Message:
-----------
linux-user: Implment host/ppc/host-signal.h
This commit re-enables ppc32 as a linux-user host,
as existance of the directory is noted by configure.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1097
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220729172141.1789105-3-richard.henderson@linaro.org>
Commit: 6aa89be5c5ff9a534280b06fad9b01604e2155cb
https://github.com/qemu/qemu/commit/6aa89be5c5ff9a534280b06fad9b01604e2155cb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M include/exec/helper-proto.h
Log Message:
-----------
tcg: Mark tcg helpers noinline to avoid an issue with LTO
Marking helpers __attribute__((noinline)) prevents an issue
with GCC's ipa-split pass under --enable-lto.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1454
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Idan Horowitz <idan.horowitz@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2e0d91513deb9bf0e5a1b2e0f574d999df3ebd99
https://github.com/qemu/qemu/commit/2e0d91513deb9bf0e5a1b2e0f574d999df3ebd99
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M disas.c
M target/loongarch/meson.build
Log Message:
-----------
target/loongarch: Enable the disassembler for host tcg
Reuse the decodetree based disassembler from
target/loongarch/ for tcg/loongarch64/.
The generation of decode-insns.c.inc into ./libcommon.fa.p/ could
eventually result in conflict, if any other host requires the same
trick, but this is good enough for now.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c2b618a8c1acb899b56eb8b2f1354da1f69474ea
https://github.com/qemu/qemu/commit/c2b618a8c1acb899b56eb8b2f1354da1f69474ea
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M target/loongarch/disas.c
M target/loongarch/insn_trans/trans_branch.c.inc
M target/loongarch/insns.decode
Log Message:
-----------
target/loongarch: Disassemble jirl properly
While jirl shares the same instruction format as bne etc,
it is not assembled the same. In particular, rd is printed
first not second and the immediate is not pc-relative.
Decode into the arg_rr_i structure, which prints correctly.
This changes the "offs" member to "imm", to update translate.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 69c9a5cfbedcaebfb0deddb5278a289629b78af5
https://github.com/qemu/qemu/commit/69c9a5cfbedcaebfb0deddb5278a289629b78af5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M target/loongarch/disas.c
Log Message:
-----------
target/loongarch: Disassemble pcadd* addresses
Print both the raw field and the resolved pc-relative
address, as we do for branches.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3fe7e36b44c0eca9b1f54060c0265c721e7f6d81
https://github.com/qemu/qemu/commit/3fe7e36b44c0eca9b1f54060c0265c721e7f6d81
Author: Rui Wang <wangrui@loongson.cn>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Optimize immediate loading
diff:
Imm Before After
0000000000000000 addi.w rd, zero, 0 addi.w rd, zero, 0
lu52i.d rd, zero, 0
00000000fffff800 lu12i.w rd, -1 addi.w rd, zero, -2048
ori rd, rd, 2048 lu32i.d rd, 0
lu32i.d rd, 0
Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221107144713.845550-1-wangrui@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 76baa33a10abaa327874d9dc4b284992e5e420c7
https://github.com/qemu/qemu/commit/76baa33a10abaa327874d9dc4b284992e5e420c7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M tcg/loongarch64/tcg-insn-defs.c.inc
Log Message:
-----------
tcg/loongarch64: Update tcg-insn-defs.c.inc
Regenerate with ADDU16I included:
$ cd loongarch-opcodes/scripts/go
$ go run ./genqemutcgdefs > $QEMU/tcg/loongarch64/tcg-insn-defs.c.inc
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0e95be93c1200ded3296654c96cb34ae13beab6d
https://github.com/qemu/qemu/commit/0e95be93c1200ded3296654c96cb34ae13beab6d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target-con-str.h
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Introduce tcg_out_addi
Adjust the constraints to allow any int32_t for immediate
addition. Split immediate adds into addu16i + addi, which
covers quite a lot of the immediate space. For the hole in
the middle, load the constant into TMP0 instead.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 21af16198425f1eaf5086e1406f22561da05e259
https://github.com/qemu/qemu/commit/21af16198425f1eaf5086e1406f22561da05e259
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Improve setcond expansion
Split out a helper function, tcg_out_setcond_int, which
does not always produce the complete boolean result, but
returns a set of flags to do so.
Accept all int32_t as constant input, so that LE/GT can
adjust the constant to LT.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7bc76a4c2e996add45291ed75ab417314a87427c
https://github.com/qemu/qemu/commit/7bc76a4c2e996add45291ed75ab417314a87427c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
Log Message:
-----------
tcg/loongarch64: Implement movcond
Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 21199bfbef8b69305cf419e22a455e7a1923c4ba
https://github.com/qemu/qemu/commit/21199bfbef8b69305cf419e22a455e7a1923c4ba
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst
Take the w^x split into account when computing the
pc-relative distance to an absolute pointer.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 709bcd7da3f6b4655d910634a0d520fa1439df38
https://github.com/qemu/qemu/commit/709bcd7da3f6b4655d910634a0d520fa1439df38
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-23 (Mon, 23 Jan 2023)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
Log Message:
-----------
tcg/loongarch64: Reorg goto_tb implementation
The old implementation replaces two insns, swapping between
b <dest>
nop
and
pcaddu18i tmp, <dest>
jirl zero, tmp, <dest> & 0xffff
There is a race condition in which a thread could be stopped at
the jirl, i.e. with the top of the address loaded, and when
restarted we have re-linked to a different TB, so that the top
half no longer matches the bottom half.
Note that while we never directly re-link to a different TB, we
can link, unlink, and link again all while the stopped thread
remains stopped.
The new implementation replaces only one insn, swapping between
b <dest>
and
pcadd tmp, <jmp_addr>
falling through to load the address from tmp, and branch.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2
https://github.com/qemu/qemu/commit/bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-03 (Fri, 03 Feb 2023)
Changed paths:
A common-user/host/ppc/safe-syscall.inc.S
M disas.c
M include/exec/helper-proto.h
M include/tcg/tcg.h
A linux-user/include/host/ppc/host-signal.h
M target/loongarch/disas.c
M target/loongarch/insn_trans/trans_branch.c.inc
M target/loongarch/insns.decode
M target/loongarch/meson.build
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target-con-str.h
M tcg/arm/tcg-target.c.inc
M tcg/loongarch64/tcg-insn-defs.c.inc
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target-con-str.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
M tcg/tcg-op.c
Log Message:
-----------
Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging
common-user: Re-enable ppc32 host
tcg: Avoid recursion in tcg_gen_mulu2_i32
tcg: Mark tcg helpers noinline to avoid an issue with LTO
tcg/arm: Use register pair allocation for qemu_{ld,st}_i64
disas: Enable loongarch disassembler, and fixes
tcg/loongarch64: Improve move immediate
tcg/loongarch64: Improve add immediate
tcg/loongarch64: Improve setcond
tcg/loongarch64: Implement movcond
tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst
tcg/loongarch64: Reorg goto_tb implementation
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# gpg: Signature made Tue 24 Jan 2023 02:01:17 GMT
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* tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu:
tcg/loongarch64: Reorg goto_tb implementation
tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst
tcg/loongarch64: Implement movcond
tcg/loongarch64: Improve setcond expansion
tcg/loongarch64: Introduce tcg_out_addi
tcg/loongarch64: Update tcg-insn-defs.c.inc
tcg/loongarch64: Optimize immediate loading
target/loongarch: Disassemble pcadd* addresses
target/loongarch: Disassemble jirl properly
target/loongarch: Enable the disassembler for host tcg
tcg: Mark tcg helpers noinline to avoid an issue with LTO
linux-user: Implment host/ppc/host-signal.h
common-user/host/ppc: Implement safe-syscall.inc.S
tcg/arm: Use register pair allocation for qemu_{ld,st}_i64
tcg: Avoid recursion in tcg_gen_mulu2_i32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/f991d61d35d0...bf4460a8d9a8
- [Qemu-commits] [qemu/qemu] 9fd86b: tcg: Avoid recursion in tcg_gen_mulu2_i32,
Peter Maydell <=