[Qemu-commits] [qemu/qemu] d1bb97: target/i386: fix cmpxchg with 32-bit register dest...

[Paolo Bonzini]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d1bb978ba1654ddc6e927621b554eebb216fb9dd
      
https://github.com/qemu/qemu/commit/d1bb978ba1654ddc6e927621b554eebb216fb9dd
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2022-11-15 (Tue, 15 Nov 2022)

  Changed paths:
    M target/i386/tcg/translate.c
    M tests/tcg/x86_64/Makefile.target
    A tests/tcg/x86_64/cmpxchg.c

  Log Message:
  -----------
  target/i386: fix cmpxchg with 32-bit register destination

Unlike the memory case, where "the destination operand receives a write
cycle without regard to the result of the comparison", rm must not be
touched altogether if the write fails, including not zero-extending
it on 64-bit processors.  This is not how the movcond currently works,
because it is always followed by a gen_op_mov_reg_v to rm.

To fix it, introduce a new function that is similar to gen_op_mov_reg_v
but writes to a TCG temporary.

Considering that gen_extu(ot, oldv) is not needed in the memory case
either, the two cases for register and memory destinations are different
enough that one might as well fuse the two "if (mod == 3)" into one.
So do that too.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/508
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[rth: Add a test case ]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 35d95e4126d83c0bb0de83007494d184f6111b3d
      
https://github.com/qemu/qemu/commit/35d95e4126d83c0bb0de83007494d184f6111b3d
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2022-11-15 (Tue, 15 Nov 2022)

  Changed paths:
    M target/i386/tcg/translate.c

  Log Message:
  -----------
  target/i386: hardcode R_EAX as destination register for LAHF/SAHF

When translating code that is using LAHF and SAHF in combination with the
REX prefix, the instructions should not use any other register than AH;
however, QEMU selects SPL (SP being register 4, just like AH) if the
REX prefix is present.  To fix this, use deposit directly without
going through gen_op_mov_v_reg and gen_op_mov_reg_v.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/130
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: dd64bcea0016938ef0be7a0c930f98b77d5e1612
      
https://github.com/qemu/qemu/commit/dd64bcea0016938ef0be7a0c930f98b77d5e1612
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-11-15 (Tue, 15 Nov 2022)

  Changed paths:
    M target/i386/tcg/translate.c
    M tests/tcg/x86_64/Makefile.target
    A tests/tcg/x86_64/cmpxchg.c

  Log Message:
  -----------
  Merge tag 'pull-x86-20221115' of https://gitlab.com/rth7680/qemu into staging

Fix cmpxchgl writeback to rax.
Fix lahf/sahf for 64-bit

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* tag 'pull-x86-20221115' of https://gitlab.com/rth7680/qemu:
  target/i386: hardcode R_EAX as destination register for LAHF/SAHF
  target/i386: fix cmpxchg with 32-bit register destination

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


Compare: https://github.com/qemu/qemu/compare/bb00d0aa620e...dd64bcea0016