[Qemu-commits] [qemu/qemu] 32bd99: MAINTAINERS: Update maintainer's email for Xilinx CAN

[Paolo Bonzini]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 32bd99d02b4549d1007fb26b7301d26c55e3ba5a
      
https://github.com/qemu/qemu/commit/32bd99d02b4549d1007fb26b7301d26c55e3ba5a
  Author: Vikram Garhwal <vikram.garhwal@amd.com>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Update maintainer's email for Xilinx CAN

Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d9721f19cd05a382f4f5a7093c80d1c4a8a1aa82
      
https://github.com/qemu/qemu/commit/d9721f19cd05a382f4f5a7093c80d1c4a8a1aa82
  Author: Jens Wiklander <jens.wiklander@linaro.org>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: fix prio masking on pmr write

With commit 39f29e599355 ("hw/intc/arm_gicv3: Use correct number of
priority bits for the CPU") the number of priority bits was changed from
the maximum value 8 to typically 5. As a consequence a few of the lowest
bits in ICC_PMR_EL1 becomes RAZ/WI. However prior to this patch one of
these bits was still used since the supplied priority value is masked
before it's eventually right shifted with one bit. So the bit is not
lost as one might expect when the register is read again.

The Linux kernel depends on lowest valid bit to be reset to zero, see
commit 33625282adaa ("irqchip/gic-v3: Probe for SCR_EL3 being clear
before resetting AP0Rn") for details.

So fix this by masking the priority value after it may have been right
shifted by one bit.

Cc: qemu-stable@nongnu.org
Fixes: 39f29e599355 ("hw/intc/arm_gicv3: Use correct number of priority bits 
for the CPU")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 98f10f0e2613ba1ac2ad3f57a5174014f6dcb03d
      
https://github.com/qemu/qemu/commit/98f10f0e2613ba1ac2ad3f57a5174014f6dcb03d
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-11-14 (Mon, 14 Nov 2022)

  Changed paths:
    M MAINTAINERS
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20221114' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/intc/arm_gicv3: fix prio masking on pmr write
 * MAINTAINERS: Update maintainer's email for Xilinx CAN

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# gpg: Signature made Mon 14 Nov 2022 10:50:15 EST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20221114' of 
https://git.linaro.org/people/pmaydell/qemu-arm:
  hw/intc/arm_gicv3: fix prio masking on pmr write
  MAINTAINERS: Update maintainer's email for Xilinx CAN

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


Compare: https://github.com/qemu/qemu/compare/305f6f62d9d2...98f10f0e2613