[Qemu-commits] [qemu/qemu] 7a0330: Merge tag 'pull-loongarch-20221104' of https://git...

[Paolo Bonzini]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 7a033008cc1865bfda3f2d6b92885439ae202009
      
https://github.com/qemu/qemu/commit/7a033008cc1865bfda3f2d6b92885439ae202009
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-11-04 (Fri, 04 Nov 2022)

  Changed paths:
    M hw/intc/loongarch_extioi.c
    M hw/intc/trace-events
    M hw/loongarch/acpi-build.c
    M hw/loongarch/virt.c
    M include/hw/loongarch/virt.h
    M include/hw/pci-host/ls7a.h
    M target/loongarch/cpu.c
    M target/loongarch/cpu.h
    M target/loongarch/insn_trans/trans_farith.c.inc
    M target/loongarch/insn_trans/trans_fcmp.c.inc
    M target/loongarch/insn_trans/trans_fmemory.c.inc
    M target/loongarch/insn_trans/trans_fmov.c.inc
    M target/loongarch/insn_trans/trans_privileged.c.inc
    M target/loongarch/iocsr_helper.c
    M target/loongarch/tlb_helper.c
    M target/loongarch/translate.c

  Log Message:
  -----------
  Merge tag 'pull-loongarch-20221104' of https://gitlab.com/gaosong/qemu into 
staging

pull-loongarch-20221104

v2:
 - fix win32 build error;
 - Add Rui Wang' patches.

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# gpg: Signature made Fri 04 Nov 2022 05:21:52 EDT
# gpg:                using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C  6C2C 40A2 FFF2 3926 3EDF

* tag 'pull-loongarch-20221104' of https://gitlab.com/gaosong/qemu:
  target/loongarch: Fix emulation of float-point disable exception
  target/loongarch: Adjust the layout of hardware flags bit fields
  target/loongarch: Fix raise_mmu_exception() set wrong exception_index
  target/loongarch: Add exception subcode
  hw/loongarch: Add TPM device for LoongArch virt machine
  hw/loongarch: Improve fdt for LoongArch virt machine
  hw/loongarch: Load FDT table into dram memory space
  hw/intc: Fix LoongArch extioi coreisr accessing
  hw/intc: Convert the memops to with_attrs in LoongArch extioi

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


  Commit: 6295a58ad1b73985b9c32d184de7d2ed1fbe1774
      
https://github.com/qemu/qemu/commit/6295a58ad1b73985b9c32d184de7d2ed1fbe1774
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-11-04 (Fri, 04 Nov 2022)

  Changed paths:
    M hw/arm/boot.c
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/sve_helper.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20221104' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Fix regression booting Trusted Firmware
 * Honor HCR_E2H and HCR_TGE in ats_write64()
 * Copy the entire vector in DO_ZIP
 * Fix Privileged Access Never (PAN) for aarch32
 * Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB
 * Set SCR_EL3.HXEn when direct booting kernel
 * Set SME and SVE EL3 vector lengths when direct booting kernel

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# gpg: Signature made Fri 04 Nov 2022 07:34:01 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20221104' of 
https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Two fixes for secure ptw
  target/arm: Honor HCR_E2H and HCR_TGE in ats_write64()
  target/arm: Copy the entire vector in DO_ZIP
  target/arm: Fix Privileged Access Never (PAN) for aarch32
  target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB
  hw/arm/boot: Set SCR_EL3.HXEn when booting kernel
  hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


Compare: https://github.com/qemu/qemu/compare/d44cf175ca71...6295a58ad1b7