[Qemu-commits] [qemu/qemu] 1c127f: pseries: Update SLOF firmware image

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 1c127fa8e2ff2b034ebf8e50faea2bbc5136afd2
      
https://github.com/qemu/qemu/commit/1c127fa8e2ff2b034ebf8e50faea2bbc5136afd2
  Author: Alexey Kardashevskiy <aik@ozlabs.ru>
  Date:   2022-01-10 (Mon, 10 Jan 2022)

  Changed paths:
    M pc-bios/README
    M pc-bios/slof.bin
    M roms/SLOF

  Log Message:
  -----------
  pseries: Update SLOF firmware image

The only change is that SLOF is compiled with -mcpu=power5
to make it work on PPC970 too.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>


  Commit: 4d805d43b2ddc5f143fb554f5e2d2da4f35ec432
      
https://github.com/qemu/qemu/commit/4d805d43b2ddc5f143fb554f5e2d2da4f35ec432
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M pc-bios/README
    M pc-bios/slof.bin
    M roms/SLOF

  Log Message:
  -----------
  Merge tag 'qemu-slof-20220110' of github.com:aik/qemu into ppc-7.0

* tag 'qemu-slof-20220110' of github.com:aik/qemu:
  pseries: Update SLOF firmware image

Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 23ab6d8813685c38fd1d87f573dded9fe37ee17f
      
https://github.com/qemu/qemu/commit/23ab6d8813685c38fd1d87f573dded9fe37ee17f
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: Add popcntb instruction to POWER5+ processors

popcntb instruction was added in ISA v2.02. Add support for POWER5+
processors since they implement ISA v2.03.

PPC970 CPUs implement v2.01 and do not support popcntb.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220105095142.3990430-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 2460e1d75ba60ee67fadabccd988705b7bb911cd
      
https://github.com/qemu/qemu/commit/2460e1d75ba60ee67fadabccd988705b7bb911cd
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Fix support of POWER5+ processors

POWER5+ (ISA v2.03) processors are supported by the pseries machine
but they do not have Altivec instructions. Do not advertise support
for it in the DT.

To be noted that this test is in contradiction with the assert in
cap_vsx_apply().

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220105095142.3990430-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 91137619c6555a3c7cdd829f3b91b6da2bf67475
      
https://github.com/qemu/qemu/commit/91137619c6555a3c7cdd829f3b91b6da2bf67475
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: Add extra float instructions to POWER5P processors

ISA v2.03 introduced Floating Round to Integer instructions : frin,
friz, frip, and frim. Add them to POWER5+.

The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal
Estimate) instruction which was introduced in ISA v2.0x. The
architecture document says its optional and that might be the reason
why it has been kept under the PPC_FLOAT_EXT flag. This means 970 CPUs
can not use it under QEMU, which doesn't seem to be a problem.

Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 808ead89a678789285d45ede951afa09413feda6
      
https://github.com/qemu/qemu/commit/808ead89a678789285d45ede951afa09413feda6
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    R docs/papr-pef.txt
    M docs/system/ppc/pseries.rst

  Log Message:
  -----------
  docs/system/ppc: Merge the PEF information into the pseries page

The Protected Execution Facility is only available with the pseries
machine, so let's merge the old ASCII text into the new RST file now.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220105103232.405204-1-thuth@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: c52887687e057f21b4b748759c2107aa7e3981b6
      
https://github.com/qemu/qemu/commit/c52887687e057f21b4b748759c2107aa7e3981b6
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Improve the PowerPC machines section

Add some documentation files to the corresponding machine sections
and mention the machine names in the section titles where it is
not so obvious (e.g. that "taihu" is a 405 machine).

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20220105104800.407570-1-thuth@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: a23a72dd1ec2695cb24dde695666d726d40823ca
      
https://github.com/qemu/qemu/commit/a23a72dd1ec2695cb24dde695666d726d40823ca
  Author: Leonardo Garcia <lagarcia@br.ibm.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M docs/specs/ppc-spapr-hcalls.rst
    M docs/system/ppc/pseries.rst

  Log Message:
  -----------
  docs: Clarifications and formatting changes in ppc docs.

Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: 
<3b228af4785241c7fb4a2c70f0c495d2a9adea83.1641405872.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: e4e27df72fba1cde2d1e030b1bedf26ca8cefe46
      
https://github.com/qemu/qemu/commit/e4e27df72fba1cde2d1e030b1bedf26ca8cefe46
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: powerpc_excp: Extract software TLB logging into a function

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107222601.4101511-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 2e089eced81e26bb6b8535776faf1bf265a0cdb4
      
https://github.com/qemu/qemu/commit/2e089eced81e26bb6b8535776faf1bf265a0cdb4
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: powerpc_excp: Keep 60x/7x5 soft MMU logs active

Remove the compile time definition and make the logging be controlled
by the `-d mmu` option in the cmdline.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220107222601.4101511-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 4dff75fe95e1aa101567d7052301f125a21323e4
      
https://github.com/qemu/qemu/commit/4dff75fe95e1aa101567d7052301f125a21323e4
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: powerpc_excp: Group unimplemented exceptions

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107222601.4101511-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 516fc1036b06a48042de1309c4e76abda255cf7b
      
https://github.com/qemu/qemu/commit/516fc1036b06a48042de1309c4e76abda255cf7b
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M target/ppc/arch_dump.c
    M target/ppc/cpu.h
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: Add HV support to ppc_interrupts_little_endian

The ppc_interrupts_little_endian function could be used for interrupts
delivered in Hypervisor mode, so add support for powernv8 and powernv9
to it.

Also drop the comment because it is inaccurate, all CPUs that can run
little endian can have interrupts in little endian. The point is
whether they can take interrupts in an endianness different from
MSR_LE.

This change has no functional impact.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220107222601.4101511-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 2e89484821883457cc76a576cf398a7efde4e052
      
https://github.com/qemu/qemu/commit/2e89484821883457cc76a576cf398a7efde4e052
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M target/ppc/cpu.h

  Log Message:
  -----------
  target/ppc: Add MSR_ILE support to ppc_interrupts_little_endian

Some CPUs set ILE via an MSR bit. We can make
ppc_interrupts_little_endian handle that case as well. Now we have a
centralized way of determining the endianness of interrupts.

This change has no functional impact.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220107222601.4101511-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 19bd7f5747dc75120f7fdaad7a153aa90d468df0
      
https://github.com/qemu/qemu/commit/19bd7f5747dc75120f7fdaad7a153aa90d468df0
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: Use ppc_interrupts_little_endian in powerpc_excp

The ppc_interrupts_little_endian function is now suitable for
determining the endianness of interrupts for all CPUs.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220107222601.4101511-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: dc88dd0a864b441453934a26a2c672f33c1d6ee7
      
https://github.com/qemu/qemu/commit/dc88dd0a864b441453934a26a2c672f33c1d6ee7
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: Introduce a wrapper for powerpc_excp

Next patches will split powerpc_excp in multiple family specific
handlers. This patch adds a wrapper to make the transition clearer.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220107222601.4101511-8-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 5609400a422809c89ea788e4d0e13124a617582e
      
https://github.com/qemu/qemu/commit/5609400a422809c89ea788e4d0e13124a617582e
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M target/ppc/arch_dump.c

  Log Message:
  -----------
  target/ppc: Set the correct endianness for powernv memory dumps

We use the endianness of interrupts to determine which endianness to
use for the guest kernel memory dump. For machines that support HILE
(powernv8 and up) we have been always generating big endian dump
files.

This patch uses the HILE support recently added to
ppc_interrupts_little_endian to fix the endianness of the dumps for
powernv machines.

Here are two dumps created at different moments:

$ file skiboot.dump
skiboot.dump: ELF 64-bit MSB core file, 64-bit PowerPC ...

$ file kernel.dump
kernel.dump: ELF 64-bit LSB core file, 64-bit PowerPC ...

Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220107222601.4101511-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 392c278302b8e20a7c593708395a6649452d323b
      
https://github.com/qemu/qemu/commit/392c278302b8e20a7c593708395a6649452d323b
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb3.c

  Log Message:
  -----------
  pnv_phb3.c: add unique chassis and slot for pnv_phb3_root_port

When creating a pnv_phb3_root_port using the command line, the first
root port is created successfully, but the second fails with the
following error:

qemu-system-ppc64: -device pnv-phb3-root-port,bus=phb3-root.0,id=pcie.3:
Can't add chassis slot, error -16

This error comes from the realize() function of its parent type,
rp_realize() from TYPE_PCIE_ROOT_PORT. pcie_chassis_add_slot() fails
with -EBUSY if there's an existing PCIESlot that has the same
chassis/slot value, regardless of being in a different bus.

One way to prevent this error is simply set chassis and slot values in
the command line. However, since phb3 root buses only supports a single
root port, we can just get an unique chassis/slot value by checking
which root bus the pnv_phb3_root_port is going to be attached, get the
equivalent phb3 device and use its chip-id and index values, which are
guaranteed to be unique.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220105212338.49899-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 5ff21d94e2ce0a89ca1a490a31929171cf28e92f
      
https://github.com/qemu/qemu/commit/5ff21d94e2ce0a89ca1a490a31929171cf28e92f
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb4.c

  Log Message:
  -----------
  pnv_phb4.c: add unique chassis and slot for pnv_phb4_root_port

A similar situation as described previously with pnv_phb3_root_port
devices also happens with pnv_phb4_root_ports.

The solution is the same: assign an unique chassis/slot combo for them.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220105212338.49899-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: a71cd51e2aae333dde272ff83661f9ef0fe62a30
      
https://github.com/qemu/qemu/commit/a71cd51e2aae333dde272ff83661f9ef0fe62a30
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb3.c
    M hw/ppc/pnv.c
    M include/hw/pci-host/pnv_phb3.h
    M include/hw/ppc/pnv.h

  Log Message:
  -----------
  ppc/pnv: Attach PHB3 root port device when defaults are enabled

This cleanups the PHB3 model a bit more since the root port is an
independent device and it will ease our task when adding user created
PHB3s.

pnv_phb_attach_root_port() is made public in pnv.c so it can be reused
with the pnv_phb4 root port later.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220105212338.49899-4-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 1360fd832b0d41b00d15574a0e9ecd6d513dbeaa
      
https://github.com/qemu/qemu/commit/1360fd832b0d41b00d15574a0e9ecd6d513dbeaa
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb4.c
    M include/hw/pci-host/pnv_phb4.h

  Log Message:
  -----------
  pnv_phb4.c: make pnv-phb4-root-port user creatable

We want to create only the absolutely minimal amount of devices when
running with -nodefaults. The root port is something that the machine
can boot up without. But, to do that, we need to provide a way for the
user to add them by hand.

This patch makes pnv-phb4-root-port user creatable and then uses the
pnv_phb_attach_root_port() helper to add a pnv_phb4_root_port only when
running with default settings.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220105212338.49899-5-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: e022e5a73a13bf1a67bb044ebbe7376c11ff4d55
      
https://github.com/qemu/qemu/commit/e022e5a73a13bf1a67bb044ebbe7376c11ff4d55
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb4.c

  Log Message:
  -----------
  pnv_phb4.c: check if root port exists in rc_config functions

pnv_phb4_rc_config_read() and pnv_phb4_rc_config_write() are asserting
the existence of the root port. The root port is now optional, and there
will be cases where a pnv-phb4 device won't have a root port attached.

Instead of asserting, check if the root port exists before read/writing
into it.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220105212338.49899-6-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 1f6a88fffc7533a9fd64c74c298d82590277cb3b
      
https://github.com/qemu/qemu/commit/1f6a88fffc7533a9fd64c74c298d82590277cb3b
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb3.c
    M hw/ppc/pnv.c
    M include/hw/ppc/pnv.h

  Log Message:
  -----------
  ppc/pnv: Introduce support for user created PHB3 devices

PHB3 devices and PCI devices can now be added to the powernv8 machine
using :

  -device pnv-phb3,chip-id=0,index=1 \
  -device nec-usb-xhci,bus=pci.1,addr=0x0

The 'index' property identifies the PHB3 in the chip. In case of user
created devices, a lookup on 'chip-id' is required to assign the
owning chip.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220105212338.49899-7-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: c29dd0034deafc9772eb256f7b4cea16c5bffd65
      
https://github.com/qemu/qemu/commit/c29dd0034deafc9772eb256f7b4cea16c5bffd65
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb3.c
    M hw/ppc/pnv.c
    M include/hw/ppc/pnv.h

  Log Message:
  -----------
  ppc/pnv: Reparent user created PHB3 devices to the PnvChip

The powernv machine uses the object hierarchy to populate the device
tree and each device should be parented to the chip it belongs to.
This is not the case for user created devices which are parented to
the container "/unattached".

Make sure a PHB3 device is parented to its chip by reparenting the
object if necessary.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220105212338.49899-8-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: db041b06e67f1010620c696011f8c867275dac42
      
https://github.com/qemu/qemu/commit/db041b06e67f1010620c696011f8c867275dac42
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb3.c
    M hw/ppc/pnv.c

  Log Message:
  -----------
  ppc/pnv: Complete user created PHB3 devices

PHB3s ared SysBus devices and should be allowed to be dynamically
created.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220105212338.49899-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: eb93c82888f4d19c00ac1aafaec23346c2e899b4
      
https://github.com/qemu/qemu/commit/eb93c82888f4d19c00ac1aafaec23346c2e899b4
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/ppc/pnv.c
    M include/hw/ppc/pnv.h

  Log Message:
  -----------
  ppc/pnv: Move num_phbs under Pnv8Chip

It is not used elsewhere so that's where it belongs.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220105212338.49899-10-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 41cb8d319df0488f31abd11519f21daf76ee1459
      
https://github.com/qemu/qemu/commit/41cb8d319df0488f31abd11519f21daf76ee1459
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M include/hw/pci-host/pnv_phb3.h

  Log Message:
  -----------
  pnv_phb3.h: change TYPE_PNV_PHB3_ROOT_BUS name

The TYPE_PNV_PHB3_ROOT_BUS name is used as the default bus name when
the dev has no 'id'. However, pnv-phb3-root-bus is a bit too long to be
used as a bus name.

Most common QEMU buses and PCI controllers are named based on their bus
type (e.g. pSeries spapr-pci-host-bridge is called 'pci'). The most
common name for a PCIE bus controller in QEMU is 'pcie'. Naming it
'pcie' would break the documented use of the pnv-phb3 device, since
'pcie.0' would now refer to the root bus instead of the first root port.

There's nothing particularly wrong with the 'root-bus' name used before,
aside from the fact that 'root-bus' is being used for pnv-phb3 and
pnv-phb4 created buses, which is not quite correct since these buses
aren't implemented the same way in QEMU - you can't plug a
pnv-phb4-root-port into a pnv-phb3 root bus, for example.

This patch renames it as 'pnv-phb3-root', which is a compromise between
the existing and the previously used name. Creating 3 phbs without ID
will result in an "info qtree" output similar to this:

bus: main-system-bus
  type System
  dev: pnv-phb3, id ""
    index = 2 (0x2)
    chip-id = 0 (0x0)
    x-config-reg-migration-enabled = true
    bypass-iommu = false
    bus: pnv-phb3-root.2
      type pnv-phb3-root
(...)
  dev: pnv-phb3, id ""
    index = 1 (0x1)
    chip-id = 0 (0x0)
    x-config-reg-migration-enabled = true
    bypass-iommu = false
    bus: pnv-phb3-root.1
      type pnv-phb3-root
(...)
  dev: pnv-phb3, id ""
    index = 0 (0x0)
    chip-id = 0 (0x0)
    x-config-reg-migration-enabled = true
    bypass-iommu = false
    bus: pnv-phb3-root.0
      type pnv-phb3-root

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220105212338.49899-11-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 451575816c07284f7620b88e2208086588288925
      
https://github.com/qemu/qemu/commit/451575816c07284f7620b88e2208086588288925
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M include/hw/pci-host/pnv_phb4.h

  Log Message:
  -----------
  pnv_phb4.c: change TYPE_PNV_PHB4_ROOT_BUS name

Similar to what was happening with pnv-phb3 buses,
TYPE_PNV_PHB4_ROOT_BUS set to "pnv-phb4-root-bus" is a bit too long for
a default root bus name. The usual default name for theses buses in QEMU
are 'pcie', but we want to make a distinction between pnv-phb4 buses and
other PCIE buses, at least as far as default name goes, because not all
PCIE devices are attachable to a pnv-phb4 root-bus type.

Changing the default to 'pnv-phb4-root' allow us to have a shorter name
while making this bus distinct, and the user can always set its own bus
naming via the "id" attribute anyway.

This is the 'info qtree' output after this change, using a powernv9
domain with 2 sockets and default settings enabled:

qemu-system-ppc64 -m 4G -machine powernv9,accel=tcg \
     -smp 2,sockets=2,cores=1,threads=1

  dev: pnv-phb4, id ""
    index = 5 (0x5)
    chip-id = 1 (0x1)
    version = 704374636546 (0xa400000002)
    device-id = 1217 (0x4c1)
    x-config-reg-migration-enabled = true
    bypass-iommu = false
    bus: pnv-phb4-root.11
      type pnv-phb4-root
      dev: pnv-phb4-root-port, id ""
(...)
  dev: pnv-phb4, id ""
    index = 0 (0x0)
    chip-id = 1 (0x1)
    version = 704374636546 (0xa400000002)
    device-id = 1217 (0x4c1)
    x-config-reg-migration-enabled = true
    bypass-iommu = false
    bus: pnv-phb4-root.6
      type pnv-phb4-root
      dev: pnv-phb4-root-port, id ""
(..)
  dev: pnv-phb4, id ""
    index = 5 (0x5)
    chip-id = 0 (0x0)
    version = 704374636546 (0xa400000002)
    device-id = 1217 (0x4c1)
    x-config-reg-migration-enabled = true
    bypass-iommu = false
    bus: pnv-phb4-root.5
      type pnv-phb4-root
      dev: pnv-phb4-root-port, id ""
(...)
  dev: pnv-phb4, id ""
    index = 0 (0x0)
    chip-id = 0 (0x0)
    version = 704374636546 (0xa400000002)
    device-id = 1217 (0x4c1)
    x-config-reg-migration-enabled = true
    bypass-iommu = false
    bus: pnv-phb4-root.0
      type pnv-phb4-root
      dev: pnv-phb4-root-port, id ""

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220110143346.455901-11-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 5032f5d70524af38259a27fb132a57cd3ca40619
      
https://github.com/qemu/qemu/commit/5032f5d70524af38259a27fb132a57cd3ca40619
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb4.c
    M hw/pci-host/pnv_phb4_pec.c
    M include/hw/pci-host/pnv_phb4.h

  Log Message:
  -----------
  pnv_phb4_pec.c: move pnv_pec_phb_offset() to pnv_phb4.c

The logic inside pnv_pec_phb_offset() will be useful in the next patch
to determine the stack that should contain a PHB4 device.

Move the function to pnv_phb4.c and make it public since there's no
pnv_phb4_pec.h header. While we're at it, add 'stack_index' as a
parameter and make the function return 'phb-id' directly. And rename it
to pnv_phb4_pec_get_phb_id() to be even clearer about the function
intent.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220110143346.455901-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: d22b0c94e4c9c5bba1224b9fd6dcc23373af0261
      
https://github.com/qemu/qemu/commit/d22b0c94e4c9c5bba1224b9fd6dcc23373af0261
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb4_pec.c

  Log Message:
  -----------
  pnv_phb4_pec: use pnv_phb4_pec_get_phb_id() in pnv_pec_dt_xscom()

Relying on stack->phb to write the xscom DT of the PEC is something that
we won't be able to do with user creatable pnv-phb4 devices.

Hopefully, this can be done by using pnv_phb4_pec_get_phb_id(), which is
already used by pnv_pec_realize() to set the phb-id of the stack. Use
the same idea in pnv_pec_dt_xscom() to write ibm,phb-index without the
need to accessing stack->phb, since stack->phb is not granted to be !=
NULL when user creatable phbs are introduced.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220110143346.455901-4-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: b580713a962ecb4b5aa928975799b8c9e970c880
      
https://github.com/qemu/qemu/commit/b580713a962ecb4b5aa928975799b8c9e970c880
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb4_pec.c

  Log Message:
  -----------
  ppc/pnv: set phb4 properties in stk_realize()

Moving all phb4 properties setup to stk_realize() keeps this logic in
a single place instead of having it scattered between stk_realize() and
pec_realize().

'phb->index' can be retrieved using stack->stack_no and
pnv_phb4_pec_get_phb_id(), deprecating the use of 'phb-id' alias that
was being used for this purpose in pec_realize().

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220111131027.599784-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 3d2adf1713b298206f831b78c00218a4e6e3ddad
      
https://github.com/qemu/qemu/commit/3d2adf1713b298206f831b78c00218a4e6e3ddad
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb4.c
    M hw/pci-host/pnv_phb4_pec.c

  Log Message:
  -----------
  ppc/pnv: move PHB4 XSCOM init to phb4_realize()

The 'stack->phb_regs_mr' PHB4 passthrough XSCOM initialization relies on
'stack->phb' being not NULL. Moving 'stack->phb_regs_mr' region_init()
and add_subregion() to phb4_realize() time is a natural thing to do
since it's strictly PHB related.

The remaining XSCOM initialization is also related to 'stack->phb' but
in a different manner. For instance, 'stack->nest_regs_mr'
MemoryRegionOps, 'pnv_pec_stk_nest_xscom_ops', uses
pnv_pec_stk_nest_xscom_write() as a write callback. When trying to write
the PEC_NEST_STK_BAR_EN reg, pnv_pec_stk_update_map() is called. Inside
this function, pnv_phb4_update_regions() is called twice. This function
uses 'stack->phb' to manipulate memory regions of the phb.

This is not a problem now but, when enabling user creatable phb4s, a
stack that doesn't have an associated phb (i.e. stack->phb = NULL) it
will cause a SIGINT during boot in pnv_phb4_update_regions().

All this can be avoided if all XSCOM realize is moved to phb4_realize(),
when we have certainty about the existence of 'stack->phb'. A lot of
code was moved from pnv_phb4_pec.c to pnv_phb4.c due to static constant
and variables being used but the cleaner logic is worth the trouble.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220111131027.599784-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: dc8e2914ab27e09ce6483fa41be6822b2ff3b650
      
https://github.com/qemu/qemu/commit/dc8e2914ab27e09ce6483fa41be6822b2ff3b650
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb4.c
    M hw/pci-host/pnv_phb4_pec.c
    M include/hw/pci-host/pnv_phb4.h

  Log Message:
  -----------
  ppc/pnv: turn 'phb' into a pointer in struct PnvPhb4PecStack

At this moment, stack->phb is the plain PnvPHB4 device itself instead of
a pointer to the device. This will present a problem when adding user
creatable devices because we can't deal with this struct and the
realize() callback from the user creatable device.

We can't get rid of this attribute, similar to what we did when enabling
pnv-phb3 user creatable devices, because pnv_phb4_update_regions() needs
to access stack->phb to do its job. This function is called twice in
pnv_pec_stk_update_map(), which is one of the nested xscom write
callbacks (via pnv_pec_stk_nest_xscom_write()). In fact,
pnv_pec_stk_update_map() code comment is explicit about how the order of
the unmap/map operations relates with the PHB subregions.

All of this indicates that this code is tied together in a way that we
either go on a crusade, featuring lots of refactories and redesign and
considerable pain, to decouple stack and phb mapping, or we allow stack
update_map operations to access the associated PHB as it is today even
after introducing pnv-phb4 user devices.

This patch chooses the latter. Instead of getting rid of stack->phb,
turn it into a PHB pointer. This will allow us to assign an user created
PHB to an existing stack later. In this process,
pnv_pec_stk_instance_init() is removed because stack->phb is being
initialized in stk_realize() instead.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220111131027.599784-4-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 5bc67b052b511ef042bd420857227e1e5173c88a
      
https://github.com/qemu/qemu/commit/5bc67b052b511ef042bd420857227e1e5173c88a
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb4.c
    M hw/pci-host/pnv_phb4_pec.c
    M hw/ppc/pnv.c

  Log Message:
  -----------
  ppc/pnv: Introduce user creatable pnv-phb4 devices

This patch introduces pnv-phb4 user creatable devices that are created
in a similar manner as pnv-phb3 devices, allowing the user to interact
with the PHBs directly instead of creating PCI Express Controllers that
will create a certain amount of PHBs per controller index.

We accomplish this by doing the following:

- add a pnv_phb4_get_stack() helper to retrieve which stack an user
created phb4 would occupy;

- when dealing with an user created pnv-phb4 (detected by checking if
phb->stack is NULL at the start of phb4_realize()), retrieve its stack
and initialize its properties as done in stk_realize();

- use 'defaults_enabled()' in stk_realize() to avoid creating and
initializing a 'stack->phb' qdev that might be overwritten by an user
created pnv-phb4 device. This process is wrapped into a new helper
called pnv_pec_stk_default_phb_realize().

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220111131027.599784-5-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 7e1e0912ec67f813473a7191274d52cab1fe476d
      
https://github.com/qemu/qemu/commit/7e1e0912ec67f813473a7191274d52cab1fe476d
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb4.c
    M include/hw/pci-host/pnv_phb4.h

  Log Message:
  -----------
  ppc/pnv: turn pnv_phb4_update_regions() into static

Its only callers are inside pnv_phb4.c.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220111131027.599784-6-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: f83460bb203a49dd1693bf8b664d2a935a5be621
      
https://github.com/qemu/qemu/commit/f83460bb203a49dd1693bf8b664d2a935a5be621
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-01-12 (Wed, 12 Jan 2022)

  Changed paths:
    M hw/pci-host/pnv_phb4.c

  Log Message:
  -----------
  ppc/pnv: use stack->pci_regs[] in pnv_pec_stk_pci_xscom_write()

pnv_pec_stk_pci_xscom_write() is pnv_pec_stk_pci_xscom_ops write
callback. It writes values into regs in the stack->nest_regs[] array.
The pnv_pec_stk_pci_xscom_read read callback, on the other hand, returns
values of the stack->pci_regs[]. In fact, at this moment, the only use
of stack->pci_regs[] is in pnv_pec_stk_pci_xscom_read(). There's no code
that is written anything in stack->pci_regs[], which is suspicious.

Considering that stack->nest_regs[] is widely used by the nested
MemoryOps pnv_pec_stk_nest_xscom_ops, in both read and write callbacks,
the conclusion is that we're writing the wrong array in
pnv_pec_stk_pci_xscom_write(). This function should write stack->pci_regs[]
instead.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220111200132.633896-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: f8d75e10d3e0033a0a29a7a7e4777a4fbc17a016
      
https://github.com/qemu/qemu/commit/f8d75e10d3e0033a0a29a7a7e4777a4fbc17a016
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-01-13 (Thu, 13 Jan 2022)

  Changed paths:
    M MAINTAINERS
    R docs/papr-pef.txt
    M docs/specs/ppc-spapr-hcalls.rst
    M docs/system/ppc/pseries.rst
    M hw/pci-host/pnv_phb3.c
    M hw/pci-host/pnv_phb4.c
    M hw/pci-host/pnv_phb4_pec.c
    M hw/ppc/pnv.c
    M hw/ppc/spapr.c
    M include/hw/pci-host/pnv_phb3.h
    M include/hw/pci-host/pnv_phb4.h
    M include/hw/ppc/pnv.h
    M pc-bios/README
    M pc-bios/slof.bin
    M roms/SLOF
    M target/ppc/arch_dump.c
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220112' into 
staging

ppc 7.0 queue:

* New SLOF for PPC970 and POWER5+ (Alexey)
* Fixes for POWER5+ pseries (Cedric)
* Updates of documentation (Leonardo and Thomas)
* First step of exception model cleanup (Fabiano)
* User created PHB3/PHB4 devices (Daniel and Cedric)

# gpg: Signature made Wed 12 Jan 2022 10:43:21 GMT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* remotes/legoater/tags/pull-ppc-20220112: (34 commits)
  ppc/pnv: use stack->pci_regs[] in pnv_pec_stk_pci_xscom_write()
  ppc/pnv: turn pnv_phb4_update_regions() into static
  ppc/pnv: Introduce user creatable pnv-phb4 devices
  ppc/pnv: turn 'phb' into a pointer in struct PnvPhb4PecStack
  ppc/pnv: move PHB4 XSCOM init to phb4_realize()
  ppc/pnv: set phb4 properties in stk_realize()
  pnv_phb4_pec: use pnv_phb4_pec_get_phb_id() in pnv_pec_dt_xscom()
  pnv_phb4_pec.c: move pnv_pec_phb_offset() to pnv_phb4.c
  pnv_phb4.c: change TYPE_PNV_PHB4_ROOT_BUS name
  pnv_phb3.h: change TYPE_PNV_PHB3_ROOT_BUS name
  ppc/pnv: Move num_phbs under Pnv8Chip
  ppc/pnv: Complete user created PHB3 devices
  ppc/pnv: Reparent user created PHB3 devices to the PnvChip
  ppc/pnv: Introduce support for user created PHB3 devices
  pnv_phb4.c: check if root port exists in rc_config functions
  pnv_phb4.c: make pnv-phb4-root-port user creatable
  ppc/pnv: Attach PHB3 root port device when defaults are enabled
  pnv_phb4.c: add unique chassis and slot for pnv_phb4_root_port
  pnv_phb3.c: add unique chassis and slot for pnv_phb3_root_port
  target/ppc: Set the correct endianness for powernv memory dumps
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/70389027d507...f8d75e10d3e0