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[Qemu-commits] [qemu/qemu] 73944a: pseries: Update SLOF firmware image
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 73944a: pseries: Update SLOF firmware image |
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Date: |
Fri, 17 Dec 2021 12:15:13 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 73944a4bf4ab259b489af8128b4aec525484d642
https://github.com/qemu/qemu/commit/73944a4bf4ab259b489af8128b4aec525484d642
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2021-11-13 (Sat, 13 Nov 2021)
Changed paths:
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
pseries: Update SLOF firmware image
This has really just one fix from Stefan, the rest is housekeeping.
The full changelog is:
Alexey Kardashevskiy (3):
Revert "make: Define default rule for .c when V=1 or V=2"
js2x: Fix compile and cleanup
version: update to 20211112
Stefan Berger (1):
tcgbios: Disable platform hierarchy in case of failure
Thomas Huth (8):
Mention the CR vs. LF problem in the documentation
slof/fs/accept: Replace TABs with spaces
Fix the URL to the Linux kernel coding style
lib/libc/README.txt: Fix "cannel" typo
travis.yml: Fix keywords
travis.yml: Update to Focal Fossa
travis.yml: Compile-test the qemu build
Silence some trivial compiler warning in the js2x code
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Commit: 2307ddc15b4f966f9de2066fe399bc723a452e28
https://github.com/qemu/qemu/commit/2307ddc15b4f966f9de2066fe399bc723a452e28
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
Merge tag 'qemu-slof-20211112' of github.com:aik/qemu into ppc-next
* tag 'qemu-slof-20211112' of github.com:aik/qemu:
pseries: Update SLOF firmware image
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 83234b8289e64fc359a5bf02d886a333d65b8f8c
https://github.com/qemu/qemu/commit/83234b8289e64fc359a5bf02d886a333d65b8f8c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
Log Message:
-----------
hw/ppc/mac.h: Remove MAX_CPUS macro
The mac.h header defines a MAX_CPUS macro. This is confusingly named,
because it suggests it's a generic setting, but in fact it's used
by only the g3beige and mac99 machines. It's also using a single
macro for two values which aren't inherently the same -- if one
of these two machines was updated to support SMP configurations
then it would want a different max_cpus value to the other.
Since the macro is used in only two places, just expand it out
and get rid of it. If hypothetical future work to support SMP
in these boards needs a compile-time-known limit on the number
of CPUs, we can give it a suitable name at that point.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211105184216.120972-1-peter.maydell@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c3a824b0cf23f98353fa91c715fe4918432d7928
https://github.com/qemu/qemu/commit/c3a824b0cf23f98353fa91c715fe4918432d7928
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Fixed call to deferred exception
mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status
after updating the value of FPSCR, but helper_float_check_status
checks fp_status and fp_status isn't updated based on FPSCR and
since the value of fp_status is reset earlier in the instruction,
it's always 0.
Because of this helper_float_check_status would change the FI bit to 0
as this bit checks if the last operation was inexact and
float_flag_inexact is always 0.
These instructions also don't throw exceptions correctly since
helper_float_check_status throw exceptions based on fp_status.
This commit created a new helper, helper_fpscr_check_status that checks
FPSCR value instead of fp_status and checks for a larger variety of
exceptions than do_float_check_status.
Since fp_status isn't used, gen_reset_fpstatus() was removed.
The hardware used to compare QEMU's behavior to was a Power9.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20211201163808.440385-2-lucas.araujo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 00d38802513da6141a732ef7c3619bd0f8f01a8e
https://github.com/qemu/qemu/commit/00d38802513da6141a732ef7c3619bd0f8f01a8e
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M tests/tcg/ppc64/Makefile.target
M tests/tcg/ppc64le/Makefile.target
A tests/tcg/ppc64le/mtfsf.c
Log Message:
-----------
test/tcg/ppc64le: test mtfsf
Added tests for the mtfsf to check if FI bit of FPSCR is being set
and if exception calls are being made correctly.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20211201163808.440385-3-lucas.araujo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 25ee608d79c1890c0f4e8c495ec8629d5712de45
https://github.com/qemu/qemu/commit/25ee608d79c1890c0f4e8c495ec8629d5712de45
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu.c
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52
This commit fixes the difference reported in the bug in the reserved
bit 52, it does this by adding this bit to the mask of bits to not be
directly altered in the ppc_store_fpscr function (the hardware used to
compare to QEMU was a Power9).
The bits 0 to 27 were also added to the mask, as they are marked as
reserved in the PowerISA and bit 28 is a reserved extension of the DRN
field (bits 29:31) but can't be set using mtfsfi, while the other DRN
bits may be set using mtfsfi instruction, so bit 28 was also added to
the mask.
Although this is a difference reported in the bug, since it's a reserved
bit it may be a "don't care" case, as put in the bug report. Looking at
the ISA it doesn't explicitly mention this bit can't be set, like it
does for FEX and VX, so I'm unsure if this is necessary.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20211201163808.440385-4-lucas.araujo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5f1470b091007f24035d6d33149df49a6dd61682
https://github.com/qemu/qemu/commit/5f1470b091007f24035d6d33149df49a6dd61682
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implement Vector Expand Mask
Implement the following PowerISA v3.1 instructions:
vexpandbm: Vector Expand Byte Mask
vexpandhm: Vector Expand Halfword Mask
vexpandwm: Vector Expand Word Mask
vexpanddm: Vector Expand Doubleword Mask
vexpandqm: Vector Expand Quadword Mask
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211203194229.746275-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 17868d81e0074905b2c1e414af6618570e8059eb
https://github.com/qemu/qemu/commit/17868d81e0074905b2c1e414af6618570e8059eb
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implement Vector Extract Mask
Implement the following PowerISA v3.1 instructions:
vextractbm: Vector Extract Byte Mask
vextracthm: Vector Extract Halfword Mask
vextractwm: Vector Extract Word Mask
vextractdm: Vector Extract Doubleword Mask
vextractqm: Vector Extract Quadword Mask
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211203194229.746275-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9193eaa901c54dbff4a91ea0b12a99e0135dbca1
https://github.com/qemu/qemu/commit/9193eaa901c54dbff4a91ea0b12a99e0135dbca1
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implement Vector Mask Move insns
Implement the following PowerISA v3.1 instructions:
mtvsrbm: Move to VSR Byte Mask
mtvsrhm: Move to VSR Halfword Mask
mtvsrwm: Move to VSR Word Mask
mtvsrdm: Move to VSR Doubleword Mask
mtvsrqm: Move to VSR Quadword Mask
mtvsrbmi: Move to VSR Byte Mask Immediate
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211203194229.746275-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ef80a708b57ddc8f605d9982bfaa0536e720ed9f
https://github.com/qemu/qemu/commit/ef80a708b57ddc8f605d9982bfaa0536e720ed9f
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/misc/ivshmem.c
Log Message:
-----------
ivshmem.c: change endianness to LITTLE_ENDIAN
The ivshmem device, as with most PCI devices, uses little endian byte
order. However, the endianness of its mmio_ops is marked as
DEVICE_NATIVE_ENDIAN. This presents not only the usual problems with big
endian hosts but also with PowerPC little endian hosts as well, since
the Power architecture in QEMU uses big endian hardware (XIVE controller,
PCI Host Bridges, etc) even if the host is in little endian byte order.
As it is today, the IVPosition of the device will be byte swapped when
running in Power BE and LE. This can be seen by changing the existing
qtest 'ivshmem-test' to run in ppc64 hosts and printing the IVPOSITION
regs in test_ivshmem_server() right after the VM ids assert. For x86_64
the VM id values read are '0' and '1', for ppc64 (tested in a Power8
RHEL 7.9 BE server) and ppc64le (tested in a Power9 RHEL 8.6 LE server)
the ids will be '0' and '0x1000000'.
Change this device to LITTLE_ENDIAN fixes the issue for Power hosts of
both endianness, and every other big-endian architecture that might use
this device, without impacting x86 users.
Fixes: cb06608e17f8 ("ivshmem: convert to memory API")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/168
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20211124092948.335389-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d04aeb6862a18540b7f72617b05be19846e1b047
https://github.com/qemu/qemu/commit/d04aeb6862a18540b7f72617b05be19846e1b047
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M tests/qtest/ivshmem-test.c
Log Message:
-----------
ivshmem-test.c: enable test_ivshmem_server for ppc64 arch
This test, if enabled by hand, was failing when the ivhsmem device was
being declared as DEVICE_NATIVE_ENDIAN with the following error:
/ppc64/ivshmem/pair: OK
/ppc64/ivshmem/server:
**
ERROR:/home/danielhb/qemu/tests/qtest/ivshmem-test.c:367:test_ivshmem_server:
assertion failed (ret != 0): (0 != 0)
Aborted
After the endianness change done in the previous patch, we can verify in
both a a Power 9 little-endian host and in a Power 8 big-endian host
that this test is now passing:
$ QTEST_QEMU_BINARY=./ppc64-softmmu/qemu-system-ppc64
./tests/qtest/ivshmem-test -m slow
/ppc64/ivshmem/single: OK
/ppc64/ivshmem/hotplug: OK
/ppc64/ivshmem/memdev: OK
/ppc64/ivshmem/pair: OK
/ppc64/ivshmem/server: OK
Let's keep it that way by officially enabling it for ppc64.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20211124092948.335389-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fa4b5eaaf923731c8667c3aec7b64ccc3c7757bf
https://github.com/qemu/qemu/commit/fa4b5eaaf923731c8667c3aec7b64ccc3c7757bf
Author: Christophe Lombard <clombard@linux.vnet.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4.c
Log Message:
-----------
pci-host: Allow extended config space access for PowerNV PHB4 model
The PCIe extended configuration space on the device is not currently
accessible to the host. if by default, it is still inaccessible for
conventional for PCIe buses, add the current flag
PCI_BUS_EXTENDED_CONFIG_SPACE on the root bus permits PCI-E extended
config space access.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211109145053.43524-1-clombard@linux.vnet.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 58c49ef5c4c367d13c51e7d488611f884fdd6ac8
https://github.com/qemu/qemu/commit/58c49ef5c4c367d13c51e7d488611f884fdd6ac8
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M docs/system/ppc/powernv.rst
Log Message:
-----------
docs: Minor updates on the powernv documentation.
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
[ clg: replaced Power9 by POWER9 ]
Message-Id:
<c387f883b3db34d9fcb44ccac2ef11c35a25e18c.1637669345.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ebe6c3fab8614a26130f7c72dd35ecede11a0f71
https://github.com/qemu/qemu/commit/ebe6c3fab8614a26130f7c72dd35ecede11a0f71
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv.c: add a friendly warning when accel=kvm is used
If one tries to use -machine powernv9,accel=kvm in a Power9 host, a
cryptic error will be shown:
qemu-system-ppc64: Register sync failed... If you're using kvm-hv.ko, only
"-cpu host" is possible
qemu-system-ppc64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid
argument
Appending '-cpu host' will throw another error:
qemu-system-ppc64: invalid chip model 'host' for powernv9 machine
The root cause is that in IBM PowerPC we have different specs for the bare-metal
and the guests. The bare-metal follows OPAL, the guests follow PAPR. The kernel
KVM modules presented in the ppc kernels implements PAPR. This means that we
can't use KVM accel when using the powernv machine, which is the emulation of
the bare-metal host.
All that said, let's give a more informative error in this case.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20211130133153.444601-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3e8f7158153f035477d975869d22d07da719f0be
https://github.com/qemu/qemu/commit/3e8f7158153f035477d975869d22d07da719f0be
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M docs/system/ppc/powernv.rst
Log Message:
-----------
docs/system/ppc/powernv.rst: document KVM support status
Put in a more accessible place the reasoning behind our decision
to officially drop KVM support in the powernv machine.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211130133153.444601-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: bbfbbff5fc0fb4cee42ed22c4430cc5d68bacc27
https://github.com/qemu/qemu/commit/bbfbbff5fc0fb4cee42ed22c4430cc5d68bacc27
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv.c: fix "system-id" FDT when -uuid is set
Setting -uuid in the pnv machine does not work:
./qemu-system-ppc64 -machine powernv8,accel=tcg -uuid
7ff61ca1-a4a0-4bc1-944c-abd114a35e80
qemu-system-ppc64: error creating device tree: (fdt_property_string(fdt,
"system-id", buf)): FDT_ERR_BADSTATE
This happens because we're using fdt_property_string(), which is a
sequential write function that is supposed to be used when we're
building a new FDT, in a case where read/writing into an existing FDT.
Fix it by using fdt_setprop_string() instead.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211207094858.744386-1-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 88581cc43b90f3e3ebf5b2a8d08916c0f2889a17
https://github.com/qemu/qemu/commit/88581cc43b90f3e3ebf5b2a8d08916c0f2889a17
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M docs/system/ppc/pseries.rst
Log Message:
-----------
docs: Introducing pseries documentation.
The purpose of this document is to substitute the content currently
available in the QEMU wiki at [0]. This initial version does contain
some additional content as well. Whenever this documentation gets
upstream and is reflected in [1], the QEMU wiki will be edited to point
to this documentation, so that we only need to keep it updated in one
place.
0. https://wiki.qemu.org/Documentation/Platforms/POWER
1. https://qemu.readthedocs.io/en/latest/system/ppc/pseries.html
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id:
<66b6fdde52062fdf4f4b4dc35a9f06a899c88293.1638981899.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d483f2b53a61753a221b85edc498552bb9dfd852
https://github.com/qemu/qemu/commit/d483f2b53a61753a221b85edc498552bb9dfd852
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M docs/specs/ppc-spapr-hcalls.txt
Log Message:
-----------
docs: rSTify ppc-spapr-hcalls.txt
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
[ clg: - replaced lingua by terminology
- add a new line at EOF ]
Message-Id:
<e20319dcf0ec37bedd915c740c3813eb0e58ead4.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d55b123d141c78cc0d965243c543a7274810da33
https://github.com/qemu/qemu/commit/d55b123d141c78cc0d965243c543a7274810da33
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
A docs/specs/ppc-spapr-hcalls.rst
R docs/specs/ppc-spapr-hcalls.txt
Log Message:
-----------
docs: Rename ppc-spapr-hcalls.txt to ppc-spapr-hcalls.rst.
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<7f13e40e05ddb411697b0777b0e37757f76905e9.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9befbe4f629d5c9b23efc347e90fed8b4d9b74e6
https://github.com/qemu/qemu/commit/9befbe4f629d5c9b23efc347e90fed8b4d9b74e6
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M docs/system/ppc/pseries.rst
Log Message:
-----------
Link new ppc-spapr-hcalls.rst file to pseries.rst.
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<7d3c8bad1ca76eb13d6ce2b16dd9a821edcdb27b.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 149a48f6e6ccedfa01307d45884aa480f5bf77c5
https://github.com/qemu/qemu/commit/149a48f6e6ccedfa01307d45884aa480f5bf77c5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Extend float_exception_flags to 16 bits
We will shortly have more than 8 bits of exceptions.
Repack the existing flags into low bits and reformat to hex.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-2-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ba11446c40903b9d97fb75a078d43fee6444d3b6
https://github.com/qemu/qemu/commit/ba11446c40903b9d97fb75a078d43fee6444d3b6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to Inf - Inf
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-3-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: bead3c9b0ff8efd652afb27923d8ab4458b3bbd9
https://github.com/qemu/qemu/commit/bead3c9b0ff8efd652afb27923d8ab4458b3bbd9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M fpu/softfloat-specialize.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to Inf * 0
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-4-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 10cc964030fca459591d9353571f3b1b4e1b5aec
https://github.com/qemu/qemu/commit/10cc964030fca459591d9353571f3b1b4e1b5aec
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flags specific to Inf / Inf and 0 / 0
PowerPC has these flags, and it's easier to compute them here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-5-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f8718aab8950c2c88c72b002aa0ba60caabfee36
https://github.com/qemu/qemu/commit/f8718aab8950c2c88c72b002aa0ba60caabfee36
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to sqrt(-x)
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-6-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 81254b02eb2a551d7794d542cbdff03e8349355e
https://github.com/qemu/qemu/commit/81254b02eb2a551d7794d542cbdff03e8349355e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to convert non-nan to int
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-7-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e706d4455b8d54252b11fc504c56df060151cb89
https://github.com/qemu/qemu/commit/e706d4455b8d54252b11fc504c56df060151cb89
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M fpu/softfloat.c
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to signaling nans
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-8-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 941298ecd7e3103d3789d2dd87dd0f119e81c69e
https://github.com/qemu/qemu/commit/941298ecd7e3103d3789d2dd87dd0f119e81c69e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_op_addsub for new flags
Now that vxisi and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-9-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 4edf55698fc2ea30903657c63ed95db0d5548943
https://github.com/qemu/qemu/commit/4edf55698fc2ea30903657c63ed95db0d5548943
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_op_mul for new flags
Now that vximz and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-10-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c07f82416cb7973c64d1e21c09957182b4b033dc
https://github.com/qemu/qemu/commit/c07f82416cb7973c64d1e21c09957182b4b033dc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_op_div for new flags
Now that vxidi, vxzdz, and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-11-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f2e25046766ed39e56d8dd5c6de790e430804511
https://github.com/qemu/qemu/commit/f2e25046766ed39e56d8dd5c6de790e430804511
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Move float_check_status from FPU_FCTI to translate
Fixes a bug in which e.g XE enabled causes inexact to be raised
before the writeback to the architectural register.
All of the users of GEN_FLOAT_B either set set_fprf, or are one
of the convert-to-integer instructions that require this behaviour.
Split out the two gen_helper_* calls in gen_compute_fprf_float64
and protect only the first with set_fprf.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-12-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 353464ea16890222fa4661717947043357b1041b
https://github.com/qemu/qemu/commit/353464ea16890222fa4661717947043357b1041b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_cvt for new flags
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-13-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fed12f3b2ddcb2ded39f48d8303c1bfc9b52772d
https://github.com/qemu/qemu/commit/fed12f3b2ddcb2ded39f48d8303c1bfc9b52772d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Fix VXCVI return value
We were returning nanval for any instance of invalid being set,
but that is an incorrect for VXCVI. This failure can be seen
in the float_convs tests.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-14-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b891757e44b4a06975f0ef59d247046f9659c690
https://github.com/qemu/qemu/commit/b891757e44b4a06975f0ef59d247046f9659c690
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Remove inline from do_fri
There's no reason the callers can't tail call to one function.
Leave it up to the compiler either way.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-15-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6bce07777755b86e7ccc27c641c580bbc69bd4eb
https://github.com/qemu/qemu/commit/6bce07777755b86e7ccc27c641c580bbc69bd4eb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Use FloatRoundMode in do_fri
This is the proper type for the enumeration.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-16-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1348d20b168b83f9400cb2bb6fca769a3a7c12ec
https://github.com/qemu/qemu/commit/1348d20b168b83f9400cb2bb6fca769a3a7c12ec
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Tidy inexact handling in do_fri
In GEN_FLOAT_B, we called helper_reset_fpstatus immediately
before calling helper_fri*. Therefore get_float_exception_flags
is known to be zero, and this code can be simplified.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-17-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a496352736033c19b530dc02c917fa5509104792
https://github.com/qemu/qemu/commit/a496352736033c19b530dc02c917fa5509104792
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Clean up do_fri
Let float64_round_to_int detect and silence snans.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-18-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e4052bb773cc829a27786d68caa22f28cff19d39
https://github.com/qemu/qemu/commit/e4052bb773cc829a27786d68caa22f28cff19d39
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update fmadd for new flags
Now that vximz, vxisi, and vxsnan are computed directly by
softfloat, we don't need to recompute it. This replaces the
separate float{32,64}_maddsub_update_excp functions with a
single float_invalid_op_madd function.
Fix VSX_MADD by passing sfprf to float_invalid_op_madd,
whereas the previous *_maddsub_update_excp assumed it true.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-19-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ffdaff8e9c698061f57a6b1827570562c5a1c909
https://github.com/qemu/qemu/commit/ffdaff8e9c698061f57a6b1827570562c5a1c909
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Split out do_fmadd
Create a common function for all of the madd helpers.
Let the compiler tail call or inline as it chooses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-20-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2125ac18bfa3e9568b75906636ec9c69c628c0a0
https://github.com/qemu/qemu/commit/2125ac18bfa3e9568b75906636ec9c69c628c0a0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Do not call do_float_check_status from do_fmadd
We will process flags other than in valid in helper_float_check_status,
which is invoked after the writeback to FRT.
Fixes a bug in which FRT is not written when OE/UE/XE are enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-21-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7238e55bd6cc494728561e7367b8068182a915c3
https://github.com/qemu/qemu/commit/7238e55bd6cc494728561e7367b8068182a915c3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Split out do_frsp
Calling helper_frsp directly from other helpers generates
the incorrect retaddr. Split out a helper that takes the
retaddr as a parameter.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-22-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 734cfbd84e6951e136aea129b37e6e3d4a58913a
https://github.com/qemu/qemu/commit/734cfbd84e6951e136aea129b37e6e3d4a58913a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update do_frsp for new flags
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-23-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 58c7edef6163dd9a136e64149b08eec3f5778f37
https://github.com/qemu/qemu/commit/58c7edef6163dd9a136e64149b08eec3f5778f37
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Use helper_todouble in do_frsp
We only needed one ieee arithmetic operation to raise
exceptions. To convert back to register form, we can
use our simpler non-arithmetic function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-24-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3d3050cc8d12ad4a59c0f0b952f8e85e0212d2b6
https://github.com/qemu/qemu/commit/3d3050cc8d12ad4a59c0f0b952f8e85e0212d2b6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update sqrt for new flags
Now that vxsqrt and vxsnan are computed directly by softfloat,
we don't need to recompute it. Split out float_invalid_op_sqrt
to be used in several places. This fixes VSX_SQRT, which did
not order its tests correctly to eliminate NaN with sign set.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-25-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 053e23a6942bc3208fff4a097483d4afce79a1ee
https://github.com/qemu/qemu/commit/053e23a6942bc3208fff4a097483d4afce79a1ee
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update xsrqpi and xsrqpxp to new flags
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-26-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8ea0b1408e680ecd08a48c51fb1e4d0ec8cbdc15
https://github.com/qemu/qemu/commit/8ea0b1408e680ecd08a48c51fb1e4d0ec8cbdc15
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update fre to new flags
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-27-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 42636fb923de0598104858d886c6f0acdbeb21b5
https://github.com/qemu/qemu/commit/42636fb923de0598104858d886c6f0acdbeb21b5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add float64r32 arithmetic routines
These variants take a float64 as input, compute the result to
infinite precision (as we do with FloatParts), round the result
to the precision and dynamic range of float32, and then return
the result in the format of float64.
This is the operation PowerPC requires for its float32 operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-28-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d04ca895dc7fec3a5d6e5a017093f807d47ce141
https://github.com/qemu/qemu/commit/d04ca895dc7fec3a5d6e5a017093f807d47ce141
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helpers for fmadds et al
Use float64r32_muladd. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-29-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 41ae890d08b2254da02c2b422a85cbb9d38843df
https://github.com/qemu/qemu/commit/41ae890d08b2254da02c2b422a85cbb9d38843df
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helper for fsqrts
Use float64r32_sqrt. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-30-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d9e792a1c17020ea87f281b83d4d79a1fda3856f
https://github.com/qemu/qemu/commit/d9e792a1c17020ea87f281b83d4d79a1fda3856f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helpers for fadds, fsubs, fdivs
Use float64r32_{add,sub,div}. Fixes a double-rounding issue with
performing the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-31-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7f87214e3b9f0d562d75f9c7315bfa53b00d29a6
https://github.com/qemu/qemu/commit/7f87214e3b9f0d562d75f9c7315bfa53b00d29a6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helper for fmuls
Use float64r32_mul. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-32-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: dedbfda765a74c3965c5dd676e64fc3afa15e963
https://github.com/qemu/qemu/commit/dedbfda765a74c3965c5dd676e64fc3afa15e963
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helper for frsqrtes
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 32, but perform the
operation with float64r32_div for consistency.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-33-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7d82ea34840e1d53bb173ad628b0f2371741d138
https://github.com/qemu/qemu/commit/7d82ea34840e1d53bb173ad628b0f2371741d138
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update fres to new flags and float64r32
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 256, but perform the
operation with float64r32_div for consistency.
Use float_flag_invalid_snan instead of recomputing the
snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-34-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a1f1c731c6515313d81630eff8867f0cba27dec5
https://github.com/qemu/qemu/commit/a1f1c731c6515313d81630eff8867f0cba27dec5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Use helper_todouble/tosingle in helper_xststdcsp
When computing the predicate "is this value currently formatted
for single precision", we do not want to round the value according
to the current rounding mode, nor perform a floating-point equality.
We want to see if the N bits that make up single-precision are the
only ones set within the register, and then a bitwise equality.
Fixes a bug in which a single-precision NaN is considered !SP,
because float64_eq(nan, nan) is always false.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-35-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1da666cd8e795295e23f6feac7cf8d06f9c64725
https://github.com/qemu/qemu/commit/1da666cd8e795295e23f6feac7cf8d06f9c64725
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Disable software TLB for the 7450 family
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447 and 7447a)*
We have since 2011 [1] been unable to run OpenBIOS in the 7450s and
have not heard of any other software that is used with those CPUs in
QEMU. A current discussion [2] shows that the 7450 software TLB is
unsupported in Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS
3.15. With no known support in firmware or OS, this means that no code
for any of the 7450 CPUs is ever ran in QEMU.
Since the implementation in QEMU of the 7400 MMU is the same as the
7450, except for the software TLB vs. hardware TLB search, this patch
changes all 7450 cpus to the 7400 MMU model. This has the practical
effect of disabling the software TLB feature while keeping other
aspects of address translation working as expected.
This allow us to run software on the 7450 family again.
*- note that the 7448 is currently aliased in QEMU for a 7400, so it
is unaffected by this change.
1- https://bugs.launchpad.net/qemu/+bug/812398
https://gitlab.com/qemu-project/qemu/-/issues/86
2- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
message id: 20211119134431.406753-1-farosas@linux.ibm.com
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b137fb72d7f41a8c7e4dacbd0394612420db6c5d
https://github.com/qemu/qemu/commit/b137fb72d7f41a8c7e4dacbd0394612420db6c5d
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Disable unused facilities in the e600 CPU
The e600 CPU is a successor of the 7448 and like all the 7450s CPUs,
it has an optional software TLB feature.
We have determined that there is no OS software support for the 7450
software TLB available these days. See the previous commit for more
information.
This patch disables the SPRs and instructions related to software TLB
from the e600 CPU.
No functional change intended. These facilities should be used by the
OS in interrupt handlers for interrupts that QEMU never generates.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a09410ed1fb80a8d5e624d93b51e46ccdafdea64
https://github.com/qemu/qemu/commit/a09410ed1fb80a8d5e624d93b51e46ccdafdea64
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Remove the software TLB model of 7450 CPUs
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448)
The QEMU-side software TLB implementation for the 7450 family of CPUs
is being removed due to lack of known users in the real world. The
last users in the code were removed by the two previous commits.
A brief history:
The feature was added in QEMU by commit 7dbe11acd8 ("Handle all MMU
models in switches...") with the mention that Linux was not able to
handle the TLB miss interrupts and the MMU model would be kept
disabled.
At some point later, commit 8ca3f6c382 ("Allow selection of all
defined PowerPC 74xx (aka G4) CPUs.") enabled the model for the 7450
family without further justification.
We have since the year 2011 [1] been unable to run OpenBIOS in the
7450s and have not heard of any other software that is used with those
CPUs in QEMU. Attempts were made to find a guest OS that implemented
the TLB miss handlers and none were found among Linux 5.15, FreeBSD 13,
MacOS9, MacOSX and MorphOS 3.15.
All CPUs that registered this feature were moved to an MMU model that
replaces the software TLB with a QEMU hardware TLB
implementation. They can now run the same software as the 7400 CPUs,
including the OSes mentioned above.
References:
- https://bugs.launchpad.net/qemu/+bug/812398
https://gitlab.com/qemu-project/qemu/-/issues/86
- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
message id: 20211119134431.406753-1-farosas@linux.ibm.com
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6328a3bb4bc57f8898eed9192546b6d0380eca73
https://github.com/qemu/qemu/commit/6328a3bb4bc57f8898eed9192546b6d0380eca73
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Fix MPCxxx FPU interrupt address
The Floating-point Unavailable and Decrementer interrupts are being
registered at the same 0x900 address. The FPU should be at 0x800
instead.
Verified on MPC555, MPC860 and MPC885 user manuals.
Reported-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fd77f75710c30416d501fa316040290e9a82960f
https://github.com/qemu/qemu/commit/fd77f75710c30416d501fa316040290e9a82960f
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove 603e exception model
The 603e uses the same exception code as 603 so we don't need a
dedicated entry for it.
This is only a removal of redundant code, no functional change.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 84835acbbfa4cb05146e218a7e5228707513d462
https://github.com/qemu/qemu/commit/84835acbbfa4cb05146e218a7e5228707513d462
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Set 601v exception model id
The exception model id for 601v has been removed without mention
why. I assume it was inadvertent and restore it here.
Fixes: b632a148b6 ("target-ppc: Use QOM method dispatch for MMU fault handling")
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c8f49e6b938e72eba2331cfce0ab20c6994ac74d
https://github.com/qemu/qemu/commit/c8f49e6b938e72eba2331cfce0ab20c6994ac74d
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu-qom.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: remove 401/403 CPUs
They have been there since 2007 without any board using them, most
were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211202191108.1291515-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 82f64c2384507477618db75d24c92b7324ff674c
https://github.com/qemu/qemu/commit/82f64c2384507477618db75d24c92b7324ff674c
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Change kernel load address
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=1000000\0"
"fdt_addr_r=1800000\0"
"ramdisk_addr_r=1900000\0"
The taihu is one of these boards, the ref405ep is not but we don't
have much information on it and both boards have a very similar
address space layout.
Also, if loaded at address 0, U-Boot will partially overwrite the
uImage because of a bug in get_ram_size() (U-Boot v2015.10) not
restoring properly the probed RAM contents and because the exception
vectors are installed in the same range. Finally, a gzipped kernel
image will be uncompressed at 0x0. These are all good reasons for not
mappping a kernel image at this address.
Change the kernel load address to match U-Boot expectations and fix
loading.
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211202191446.1292125-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 26e8bed611222c4e2b9408a8d5a405158e491a98
https://github.com/qemu/qemu/commit/26e8bed611222c4e2b9408a8d5a405158e491a98
Author: Thomas Huth <thuth@redhat.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M docs/about/deprecated.rst
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc: Mark the 'taihu' machine as deprecated
The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
except for some external periphery. However, the periphery of the 'taihu'
machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
been implemented), so there is not much value added by this board. The users
can use the 'ref405ep' machine to test their PPC405 code instead.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211203164904.290954-2-thuth@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: de82dabeadd0511a3b18c76dc3c666a63798f8ae
https://github.com/qemu/qemu/commit/de82dabeadd0511a3b18c76dc3c666a63798f8ae
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc.c
M hw/ppc/trace-events
Log Message:
-----------
ppc: Add trace-events for DCR accesses
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 09960a5be3ec4b8caddb894ad5b73d4533ead5fb
https://github.com/qemu/qemu/commit/09960a5be3ec4b8caddb894ad5b73d4533ead5fb
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405_uc.c
M hw/ppc/trace-events
Log Message:
-----------
ppc/ppc405: Convert printfs to trace-events
and one error message to a LOG_GUEST_ERROR.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: af9e361512a39f1b9a6b29a838656dbeb8fa7233
https://github.com/qemu/qemu/commit/af9e361512a39f1b9a6b29a838656dbeb8fa7233
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo()
It was introduced in commit b8d3f5d12642 ("Add flags to support
PowerPC 405 bootinfos variations.") but since its value has always
been set to '1'.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a3e973e1bfffb2cddfc0763fe90414f8ca3bf531
https://github.com/qemu/qemu/commit/a3e973e1bfffb2cddfc0763fe90414f8ca3bf531
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Change ppc405ep_init() return value
I will be useful to rework the boot from Linux.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f61b99d35e31d98f1799cdfdf14ec96093e903a5
https://github.com/qemu/qemu/commit/f61b99d35e31d98f1799cdfdf14ec96093e903a5
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Add some address space definitions
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9fb100efa169749da9f148440e3b1005345fb6d8
https://github.com/qemu/qemu/commit/9fb100efa169749da9f148440e3b1005345fb6d8
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Remove flash support
It is currently impossible to find a "ppc405_rom.bin" firmware file or
a full flash image for the PPC405EP evalution board. Even if it should
be technically possible to recreate such an image, it's unlikely that
anyone will do it since the board is obsolete and support in QEMU has
been broken for about 10 years.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 13d63de59bf31119f3d47e638a64b27da86e1a5f
https://github.com/qemu/qemu/commit/13d63de59bf31119f3d47e638a64b27da86e1a5f
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Rework FW load
QEMU installs a custom U-Boot in-memory descriptor to share board
information with Linux, which means that the QEMU machine was
initially designed to support booting Linux directly without using the
loaded FW. But, it's not that simple because the CPU still starts at
address 0xfffffffc where nothing is currently mapped. Support must
have been broken these last years.
Since we can not find a "ppc405_rom.bin" firmware file, request one to
be specified on the command line. A consequence of this change is that
the machine can be booted directly from Linux without any FW being
loaded. This is still broken and the CPU start address will be fixed
in the next changes.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e3931ecab32d993fa89802b3a8af39f3ea957b3d
https://github.com/qemu/qemu/commit/e3931ecab32d993fa89802b3a8af39f3ea957b3d
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Introduce ppc405_set_default_bootinfo()
This routine is a small helper to cleanup the code. The update of the
flash fields were removed because there are not of any use when booting
from a Linux kernel image. It should be functionally equivalent.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 337270b2a5b7e23fd595aaf22a789bf3194887cd
https://github.com/qemu/qemu/commit/337270b2a5b7e23fd595aaf22a789bf3194887cd
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Fix boot from kernel
The machine can already boot with kernel and initrd U-boot images if a
firmware is loaded first. Adapt and improve the load sequence to let
the machine boot directly from a Linux kernel ELF image and a usual
initrd image if a firmware image is not provided. For that, install a
custom CPU reset handler to setup the registers and to start the CPU
from the Linux kernel entry point.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-12-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: cada9f30d35ccbd613ade00c4986a74a5446aa21
https://github.com/qemu/qemu/commit/cada9f30d35ccbd613ade00c4986a74a5446aa21
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Change default PLL values at reset
These values are computed and updated by U-Boot at startup. Use them
as defaults to improve direct Linux boot.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-13-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e0caa8e64de2c62dfa00afc176e2dd2b3afe7f19
https://github.com/qemu/qemu/commit/e0caa8e64de2c62dfa00afc176e2dd2b3afe7f19
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
Log Message:
-----------
ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information
The board information for the 405EP first appeared in commit 04f20795ac81
("Move PowerPC 405 specific definitions into a separate file ...")
An Ethernet address is a 6 byte number. Fix that.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-14-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6518c0ede9f8b12c7eb4ab5e843bcacb7198652f
https://github.com/qemu/qemu/commit/6518c0ede9f8b12c7eb4ab5e843bcacb7198652f
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Add update of bi_procfreq field
Adapt the fields offset in the board information for Linux. Since
Linux relies on the CPU frequency value, I wonder how it ever worked.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-15-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 201fc774e0e1cc76ec23b595968004a7b14fb6e8
https://github.com/qemu/qemu/commit/201fc774e0e1cc76ec23b595968004a7b14fb6e8
Author: Victor Colombo <victor.colombo@eldorado.org.br>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Fix xs{max, min}[cj]dp to use VSX registers
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using
vector registers when they should be using VSX ones. This happens
because the instructions are using GEN_VSX_HELPER_R3, which adds 32
to the register numbers, effectively making them vector registers.
This patch fixes it by changing these instructions to use
GEN_VSX_HELPER_X3.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20211213120958.24443-2-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c5df1898a147c232f0502cda5dac8df6074070fc
https://github.com/qemu/qemu/commit/c5df1898a147c232f0502cda5dac8df6074070fc
Author: Victor Colombo <victor.colombo@eldorado.org.br>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Move xs{max,min}[cj]dp to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20211213120958.24443-3-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 38d4914c5065e14f0969161274793ded448f067f
https://github.com/qemu/qemu/commit/38d4914c5065e14f0969161274793ded448f067f
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: fix xscvqpdp register access
This instruction has VRT and VRB fields instead of T/TX and B/BX.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211213120958.24443-4-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: caf6f9b568479bea6f6d97798be670f21641a006
https://github.com/qemu/qemu/commit/caf6f9b568479bea6f6d97798be670f21641a006
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: move xscvqpdp to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211213120958.24443-5-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7fc1dc8313219182bc279ad1861d34b3fc27fa25
https://github.com/qemu/qemu/commit/7fc1dc8313219182bc279ad1861d34b3fc27fa25
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Fix e6500 boot
When Altivec support was added to the e6500 kernel in 2012[1], the
QEMU code was not changed, so we don't register the VPU/VPUA
exceptions for the e6500:
qemu: fatal: Raised an exception without defined vector 73
Note that the error message says 73, instead of 32, which is the IVOR
for VPU. This is because QEMU knows only knows about the VPU interrupt
for the 7400s. In theory, we should not be raising _that_ VPU
interrupt, but instead another one specific for the e6500.
We unfortunately cannot register e6500-specific VPU/VPUA interrupts
because the SPEU/EFPDI interrupts also use IVOR32/33. These are
present only in the e500v1/2 versions. From the user manual:
e500v1, e500v2: only SPEU/EFPDI/EFPRI
e500mc, e5500: no SPEU/EFPDI/EFPRI/VPU/VPUA
e6500: only VPU/VPUA
So I'm leaving IVOR32/33 as SPEU/EFPDI, but altering the dispatch code
to convert the VPU #73 to a #32 when we're in the e6500. Since the
handling for SPEU and VPU is the same this is the only change that's
needed. The EFPDI is not implemented and will cause an abort. I don't
think it worth it changing the error message to take VPUA into
consideration, so I'm not changing anything there.
This bug was discussed in the thread:
https://lists.gnu.org/archive/html/qemu-ppc/2021-06/msg00222.html
1- https://git.kernel.org/torvalds/c/cd66cc2ee52
Reported-by: <mario@locati.it>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213133542.2608540-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 29c4a3363bf287bb9a7b0342b1bc2dba3661c96c
https://github.com/qemu/qemu/commit/29c4a3363bf287bb9a7b0342b1bc2dba3661c96c
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp"
This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2.
It breaks the --disable-tcg build:
../target/ppc/excp_helper.c:463:29: error: implicit declaration of
function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration]
We should not have TCG code in powerpc_excp because some kvm-only
routines use it indirectly to dispatch interrupts. See
kvm_handle_debug, spapr_mce_req_event and
spapr_do_system_reset_on_cpu.
We can re-introduce the change once we have split the interrupt
injection code between KVM and TCG.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20211209173323.2166642-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8f2e9d400320d75bb54d693282672cc407d8a128
https://github.com/qemu/qemu/commit/8f2e9d400320d75bb54d693282672cc407d8a128
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/spapr_cpu_core.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/meson.build
A target/ppc/power8-pmu.c
A target/ppc/power8-pmu.h
Log Message:
-----------
target/ppc: introduce PMUEventType and PMU overflow timers
This patch starts an IBM Power8+ compatible PMU implementation by adding
the representation of PMU events that we are going to sample,
PMUEventType. This enum represents a Perf event that is being sampled by
a specific counter 'sprn'. Events that aren't available (i.e. no event
was set in MMCR1) will be of type 'PMU_EVENT_INVALID'. Events that are
inactive due to frozen counter bits state are of type
'PMU_EVENT_INACTIVE'. Other types added in this patch are
PMU_EVENT_CYCLES and PMU_EVENT_INSTRUCTIONS. More types will be added
later on.
Let's also add the required PMU cycle overflow timers. They will be used
to trigger cycle overflows when cycle events are being sampled. This
timer will call cpu_ppc_pmu_timer_cb(), which in turn calls
fire_PMC_interrupt(). Both functions are stubs that will be implemented
later on when EBB support is added.
Two new helper files are created to host this new logic.
cpu_ppc_pmu_init() will init all overflow timers during CPU init time.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c2eff582a32f4251515e041f4919d3fbe4a0048e
https://github.com/qemu/qemu/commit/c2eff582a32f4251515e041f4919d3fbe4a0048e
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
Log Message:
-----------
target/ppc: PMU basic cycle count for pseries TCG
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 308b9fad2a301f3473e920f981d49e2ff0829029
https://github.com/qemu/qemu/commit/308b9fad2a301f3473e920f981d49e2ff0829029
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
Log Message:
-----------
target/ppc: PMU: update counters on PMCs r/w
Calling pmu_update_cycles() on every PMC read/write operation ensures
that the values being fetched are up to date with the current PMU state.
In theory we can get away by just trapping PMCs reads, but we're going
to trap PMC writes to deal with counter overflow logic later on. Let's
put the required wiring for that and make our lives a bit easier in the
next patches.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-4-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a6f91249e064a2ee935c900529b03f949ad89e6c
https://github.com/qemu/qemu/commit/a6f91249e064a2ee935c900529b03f949ad89e6c
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
Log Message:
-----------
target/ppc: PMU: update counters on MMCR1 write
MMCR1 determines the events to be sampled by the PMU. Updating the
counters at every MMCR1 write ensures that we're not sampling more
or less events by looking only at MMCR0 and the PMCs.
It is worth noticing that both the Book3S PowerPC PMU, and this IBM
Power8+ PMU that we're modeling, also uses MMCRA, MMCR2 and MMCR3 to
control the PMU. These three registers aren't being handled in this
initial implementation, so for now we're controlling all the PMU
aspects using MMCR0, MMCR1 and the PMCs.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-5-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1474ba6d100179c248fed6c67756814a6fa89432
https://github.com/qemu/qemu/commit/1474ba6d100179c248fed6c67756814a6fa89432
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/power8-pmu.c
Log Message:
-----------
target/ppc: enable PMU counter overflow with cycle events
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert
can trigger an event-based exception (to be implemented in the next patches)
if the MMCR0_EBE bit is set.
For now, overflowing the counter when the PMC is counting cycles will
just trigger a performance monitor alert. This is done by starting the
overflow timer to expire in the moment the overflow would be occuring. The
timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will
trigger the PMU alert and, if the conditions are met, an EBB exception.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-6-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 46d396bde988020528445691089711eb27b348b5
https://github.com/qemu/qemu/commit/46d396bde988020528445691089711eb27b348b5
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: enable PMU instruction count
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions (Perf
event PM_INST_CMPL) by counting the amount of instructions translated in
each translation block right before exiting it.
A new pmu_count_insns() helper in translation.c was added to do that.
After verifying that the PMU is counting instructions, call
helper_insns_inc(). This new helper from power8-pmu.c will add the
instructions to the relevant counters. It'll also be responsible for
triggering counter negative overflows as it is already being done with
cycles.
To verify whether the PMU is counting instructions or now, a new hflags
named 'HFLAGS_INSN_CNT' is introduced. This flag will match the internal
state of the PMU. We're be using this flag to avoid calling
helper_insn_inc() when we do not have a valid instruction event being
sampled.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-7-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7aeac354a6925afcec684e985d56e612f9e81b2d
https://github.com/qemu/qemu/commit/7aeac354a6925afcec684e985d56e612f9e81b2d
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time SPR_CTRL is written. A small tweak in
pmu_increment_insns() is then needed to only increment this event
if the thread has the run latch.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-8-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1f26c75191178a9c652bc98afbefa00c0d4fb486
https://github.com/qemu/qemu/commit/1f26c75191178a9c652bc98afbefa00c0d4fb486
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate.c
A target/ppc/translate/branch-impl.c.inc
Log Message:
-----------
PPC64/TCG: Implement 'rfebb' instruction
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.
The following operations happens during an EBB:
- Global Enable (GE) bit of BESCR is set to 0;
- bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set
to the the effective address of the NIA that would have executed if the EBB
didn't happen;
- Instruction fetch and execution will continue in the effective address
contained in the Event-Based Branch Handler Register (EBBHR).
The EBB Handler will process the event and then execute the Return From
Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then
redirects execution to the address pointed in EBBRR. This process is
described in the PowerISA v3.1, Book II, Chapter 6 [1].
This patch implements the rfebb instruction. Descriptions of all
relevant BESCR bits are also added - this patch is only using BESCR_GE,
but the next patches will use the remaining bits.
[1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2c4d3a501e55bb90f90577b2e3f0181dc89efd42
https://github.com/qemu/qemu/commit/2c4d3a501e55bb90f90577b2e3f0181dc89efd42
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb3.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb3.h
Log Message:
-----------
ppc/pnv: Introduce a "chip" property under PHB3
This change will help us move the mapping of XSCOM regions under the
PHB3 realize routine, which will be necessary for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a8fa95c7e621d3cd0dddb653b4f894fac65dec19
https://github.com/qemu/qemu/commit/a8fa95c7e621d3cd0dddb653b4f894fac65dec19
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb3.c
Log Message:
-----------
ppc/pnv: Use the chip class to check the index of PHB3 devices
The maximum number of PHB3 devices per chip can be different depending
on the POWER8 processor model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9e59b09ccf7c3cb0ac666a63f4883f1389b68465
https://github.com/qemu/qemu/commit/9e59b09ccf7c3cb0ac666a63f4883f1389b68465
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Drop the "num-phbs" property
It is never used.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 10841a76eb8900ab5718fe91beb6f73ec365291a
https://github.com/qemu/qemu/commit/10841a76eb8900ab5718fe91beb6f73ec365291a
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb3_pbcq.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize()
This change will help us providing support for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2ff73dda02d8a467ab56a0e497df7888a15af0c3
https://github.com/qemu/qemu/commit/2ff73dda02d8a467ab56a0e497df7888a15af0c3
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Use QOM hierarchy to scan PHB3 devices
When -nodefaults is supported for PHB3 devices, the phbs array under
the chip will be empty. This will break the XICSFabric handlers, and
all interrupt delivery, and the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PHB3 devices instead.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 422fd92e613ab6b5239538bf2dc1202eb9d3f0f5
https://github.com/qemu/qemu/commit/422fd92e613ab6b5239538bf2dc1202eb9d3f0f5
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribute represents better the logic units of the
POWER9 chip. Use that instead of num_phbs which fits POWER8 chips.
This will ease adding support for user created devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 12060cbd3fd42e2a263c473829f5872c89dc71d7
https://github.com/qemu/qemu/commit/12060cbd3fd42e2a263c473829f5872c89dc71d7
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: Introduce version and device_id class atributes for PHB4 devices
It prepares ground for PHB5 which has different values.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6f43d2551fba2569e67c8c1ac4e8768a566738eb
https://github.com/qemu/qemu/commit/6f43d2551fba2569e67c8c1ac4e8768a566738eb
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: Introduce a "chip" property under the PHB4 model
And check the PEC index using the chip class.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: cf0ee6955cc2f7f256e44c4f8198f69aae6ea39c
https://github.com/qemu/qemu/commit/cf0ee6955cc2f7f256e44c4f8198f69aae6ea39c
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: Introduce a num_stack class attribute
Each PEC device of the POWER9 chip has a predefined number of stacks,
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove the
"num-stacks" property.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: aa8cc84d88945088e4588aeaa31573fb4ed3b27a
https://github.com/qemu/qemu/commit/aa8cc84d88945088e4588aeaa31573fb4ed3b27a
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Compute the PHB index from the PHB4 PEC model
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
The routine pnv_pec_phb_offset() is a bit complex but it also prepares
ground for PHB5 which has a different layout of stacks: 3 per PECs.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-12-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8da4f8f7b7e7ab896834130a139528e4b1c0b446
https://github.com/qemu/qemu/commit/8da4f8f7b7e7ab896834130a139528e4b1c0b446
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Remove "system-memory" property from PHB4 PEC
This is not useful and will be in the way for support of user created
PHB4 devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-13-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 13480fc58a57e5274894cdb87120fd49c9c95ddc
https://github.com/qemu/qemu/commit/13480fc58a57e5274894cdb87120fd49c9c95ddc
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Move realize of PEC stacks under the PEC model
This change will help us providing support for user created PHB4
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-14-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0e6232bc3cb96bdf6fac1b5d7659aa9887afe657
https://github.com/qemu/qemu/commit/0e6232bc3cb96bdf6fac1b5d7659aa9887afe657
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices
When -nodefaults is supported for PHB4 devices, the pecs array under
the chip will be empty. This will break the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PEC PHB4 devices
instead.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-15-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 93dc314c9225e103487ae22b62da1ac59ac86325
https://github.com/qemu/qemu/commit/93dc314c9225e103487ae22b62da1ac59ac86325
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-17 (Fri, 17 Dec 2021)
Changed paths:
M docs/about/deprecated.rst
A docs/specs/ppc-spapr-hcalls.rst
R docs/specs/ppc-spapr-hcalls.txt
M docs/system/ppc/powernv.rst
M docs/system/ppc/pseries.rst
M fpu/softfloat-parts.c.inc
M fpu/softfloat-specialize.c.inc
M fpu/softfloat.c
M hw/misc/ivshmem.c
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb3_pbcq.c
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
M hw/ppc/pnv.c
M hw/ppc/ppc.c
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/trace-events
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
M include/hw/pci-host/pnv_phb3.h
M include/hw/pci-host/pnv_phb4.h
M include/hw/ppc/pnv.h
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu-qom.h
M target/ppc/cpu.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/insn32.decode
M target/ppc/meson.build
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/power8-pmu-regs.c.inc
A target/ppc/power8-pmu.c
A target/ppc/power8-pmu.h
M target/ppc/spr_tcg.h
M target/ppc/translate.c
A target/ppc/translate/branch-impl.c.inc
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
M tests/qtest/ivshmem-test.c
M tests/tcg/ppc64/Makefile.target
M tests/tcg/ppc64le/Makefile.target
A tests/tcg/ppc64le/mtfsf.c
Log Message:
-----------
Merge tag 'pull-ppc-20211217' of https://github.com/legoater/qemu into staging
ppc 7.0 queue:
* General cleanup for Mac machines (Peter)
* Fixes for FPU exceptions (Lucas)
* Support for new ISA31 instructions (Matheus)
* Fixes for ivshmem (Daniel)
* Cleanups for PowerNV PHB (Christophe and Cedric)
* Updates of PowerNV and pSeries documentation (Leonardo and Daniel)
* Fixes for PowerNV (Daniel)
* Large cleanup of FPU implementation (Richard)
* Removal of SoftTLBs support for PPC74x CPUs (Fabiano)
* Fixes for exception models in MPCx and 60x CPUs (Fabiano)
* Removal of 401/403 CPUs (Cedric)
* Deprecation of taihu machine (Thomas)
* Large rework of PPC405 machine (Cedric)
* Fixes for VSX instructions (Victor and Matheus)
* Fix for e6500 CPU (Fabiano)
* Initial support for PMU (Daniel)
# gpg: Signature made Fri 17 Dec 2021 09:20:31 AM PST
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-ppc-20211217' of https://github.com/legoater/qemu: (101 commits)
ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices
ppc/pnv: Move realize of PEC stacks under the PEC model
ppc/pnv: Remove "system-memory" property from PHB4 PEC
ppc/pnv: Compute the PHB index from the PHB4 PEC model
ppc/pnv: Introduce a num_stack class attribute
ppc/pnv: Introduce a "chip" property under the PHB4 model
ppc/pnv: Introduce version and device_id class atributes for PHB4 devices
ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices
ppc/pnv: Use QOM hierarchy to scan PHB3 devices
ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize()
ppc/pnv: Drop the "num-phbs" property
ppc/pnv: Use the chip class to check the index of PHB3 devices
ppc/pnv: Introduce a "chip" property under PHB3
PPC64/TCG: Implement 'rfebb' instruction
target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event
target/ppc: enable PMU instruction count
target/ppc: enable PMU counter overflow with cycle events
target/ppc: PMU: update counters on MMCR1 write
target/ppc: PMU: update counters on PMCs r/w
target/ppc: PMU basic cycle count for pseries TCG
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/48c03a0e13f4...93dc314c9225