qemu-commits
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] 9925c8: hw/riscv: virt: Don't use a macro for


From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 9925c8: hw/riscv: virt: Don't use a macro for the PLIC con...
Date: Fri, 29 Oct 2021 11:04:43 -0700

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 9925c8bb81d34339ea0433192fdb1d58c12b8edb
      
https://github.com/qemu/qemu/commit/9925c8bb81d34339ea0433192fdb1d58c12b8edb
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  hw/riscv: virt: Don't use a macro for the PLIC configuration

Using a macro for the PLIC configuration doesn't make the code any
easier to read. Instead it makes it harder to figure out what is going
on, so let's remove it.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20211022060133.3045020-1-alistair.francis@opensource.wdc.com


  Commit: bf357e1d72cd8b7b590518dacdf4b65beb2c61e2
      
https://github.com/qemu/qemu/commit/bf357e1d72cd8b7b590518dacdf4b65beb2c61e2
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M hw/riscv/boot.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: boot: Add a PLIC config string function

Add a generic function that can create the PLIC strings.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211022060133.3045020-2-alistair.francis@opensource.wdc.com


  Commit: 4e8fb53c0b58cbb18cd243a5b067e4f26db83f77
      
https://github.com/qemu/qemu/commit/4e8fb53c0b58cbb18cd243a5b067e4f26db83f77
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv: sifive_u: Use the PLIC config helper function

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211022060133.3045020-3-alistair.francis@opensource.wdc.com


  Commit: 8486eb8cdcd336de8ae52d95da45af97f54db63e
      
https://github.com/qemu/qemu/commit/8486eb8cdcd336de8ae52d95da45af97f54db63e
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M hw/riscv/microchip_pfsoc.c
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/riscv: microchip_pfsoc: Use the PLIC config helper function

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211022060133.3045020-4-alistair.francis@opensource.wdc.com


  Commit: 7d10ff8a4de7a9bff1e7b25011f5eb43f24a6713
      
https://github.com/qemu/qemu/commit/7d10ff8a4de7a9bff1e7b25011f5eb43f24a6713
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Use the PLIC config helper function

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211022060133.3045020-5-alistair.francis@opensource.wdc.com


  Commit: 9b144ed444f1fb3149d9ec17f0c4a64d4fd7d662
      
https://github.com/qemu/qemu/commit/9b144ed444f1fb3149d9ec17f0c4a64d4fd7d662
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M hw/riscv/opentitan.c

  Log Message:
  -----------
  hw/riscv: opentitan: Fixup the PLIC context addresses

Fixup the PLIC context address to correctly support the threshold and
claim register.

Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211025040657.262696-1-alistair.francis@opensource.wdc.com


  Commit: 53dcea58b8ab150ab034f9c19074c5f74d6ca41e
      
https://github.com/qemu/qemu/commit/53dcea58b8ab150ab034f9c19074c5f74d6ca41e
  Author: Alexey Baturo <baturo.alexey@gmail.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add J-extension into RISC-V

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211025173609.2724490-2-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 138b5c5f8f5abec5acc18d2a256f0a082dc51ef5
      
https://github.com/qemu/qemu/commit/138b5c5f8f5abec5acc18d2a256f0a082dc51ef5
  Author: Alexey Baturo <baturo.alexey@gmail.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-3-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4bbe8033fcd08769cef49f5149c5c165594ae10a
      
https://github.com/qemu/qemu/commit/4bbe8033fcd08769cef49f5149c5c165594ae10a
  Author: Alexey Baturo <baturo.alexey@gmail.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Support CSRs required for RISC-V PM extension except for the 
h-mode

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-4-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b1c279e135e0da33a06544919c2cb89b6988e874
      
https://github.com/qemu/qemu/commit/b1c279e135e0da33a06544919c2cb89b6988e874
  Author: Alexey Baturo <baturo.alexey@gmail.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Add J extension state description

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-5-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bd5594ca2808b3e353d350a08d72f36cb8e01048
      
https://github.com/qemu/qemu/commit/bd5594ca2808b3e353d350a08d72f36cb8e01048
  Author: Alexey Baturo <baturo.alexey@gmail.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-6-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c655df7fe00669ac9ac3b0614be6e4a6f5782737
      
https://github.com/qemu/qemu/commit/c655df7fe00669ac9ac3b0614be6e4a6f5782737
  Author: Alexey Baturo <baturo.alexey@gmail.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of 
instructions

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-7-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0774a7a1ff24d6b8c2f90b9c341f057914b18134
      
https://github.com/qemu/qemu/commit/0774a7a1ff24d6b8c2f90b9c341f057914b18134
  Author: Anatoly Parshintsev <kupokupokupopo@gmail.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Implement address masking functions required for RISC-V Pointer 
Masking extension

Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-8-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0ee9a4e57e1cee4577cab22f6ced6c0c34fb2d94
      
https://github.com/qemu/qemu/commit/0ee9a4e57e1cee4577cab22f6ced6c0c34fb2d94
  Author: Alexey Baturo <baturo.alexey@gmail.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211025173609.2724490-9-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 487a99551ae903fc83a878d4cbc6d853e17ad252
      
https://github.com/qemu/qemu/commit/487a99551ae903fc83a878d4cbc6d853e17ad252
  Author: Jose Martins <josemartins90@gmail.com>
  Date:   2021-10-29 (Fri, 29 Oct 2021)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: fix VS interrupts forwarding to HS

VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when
not delegated in hideleg (which was not being taken into account). This
was mainly because hs level sie was not always considered enabled when
it should. The spec states that "Interrupts for higher-privilege modes,
y>x, are always globally enabled regardless of the setting of the global
yIE bit for the higher-privilege mode." and also "For purposes of
interrupt global enables, HS-mode is considered more privileged than
VS-mode, and VS-mode is considered more privileged than VU-mode". Also,
vs-level interrupts were not being taken into account unless V=1, but
should be unless delegated.

Finally, there is no need for a special case for to handle vs interrupts
as the current privilege level, the state of the global ie and of the
delegation registers should be enough to route all interrupts to the
appropriate privilege level in riscv_cpu_do_interrupt.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211026145126.11025-2-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 50d160876414e91e51ac718ac6edea6dbadf4694
      
https://github.com/qemu/qemu/commit/50d160876414e91e51ac718ac6edea6dbadf4694
  Author: Jose Martins <josemartins90@gmail.com>
  Date:   2021-10-29 (Fri, 29 Oct 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: remove force HS exception

There is no need to "force an hs exception" as the current privilege
level, the state of the global ie and of the delegation registers should
be enough to route the interrupt to the appropriate privilege level in
riscv_cpu_do_interrupt. The is true for both asynchronous and
synchronous exceptions, specifically, guest page faults which must be
hardwired to zero hedeleg. As such the hs_force_except mechanism can be
removed.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211026145126.11025-3-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0e9030376e1a8eb6d15cb5e69dffa09a6ff16b92
      
https://github.com/qemu/qemu/commit/0e9030376e1a8eb6d15cb5e69dffa09a6ff16b92
  Author: Chih-Min Chao <chihmin.chao@sifive.com>
  Date:   2021-10-29 (Fri, 29 Oct 2021)

  Changed paths:
    M fpu/softfloat-parts.c.inc
    M fpu/softfloat.c
    M include/fpu/softfloat.h

  Log Message:
  -----------
  softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin

For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN,

  The original logic:
    Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan.

  The alternative path:
    Set invalid flag if ft1 == sNaN || ft2 == sNaN.
    Return NaN only if ft1 == NaN && ft2 == NaN.

The IEEE 754 spec allows both implementation and some architecture such
as riscv choose different defintions in two spec versions.
(riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to
 alternative)

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211021160847.2748577-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 15161e425ee1bb1180f9cec574cda44fb10c0931
      
https://github.com/qemu/qemu/commit/15161e425ee1bb1180f9cec574cda44fb10c0931
  Author: Chih-Min Chao <chihmin.chao@sifive.com>
  Date:   2021-10-29 (Fri, 29 Oct 2021)

  Changed paths:
    M target/riscv/fpu_helper.c

  Log Message:
  -----------
  target/riscv: change the api for RVF/RVD fmin/fmax

The sNaN propagation behavior has been changed since cd20cee7 in
https://github.com/riscv/riscv-isa-manual.

In Priv spec v1.10, RVF is v2.0. fmin.s and fmax.s are implemented with
IEEE 754-2008 minNum and maxNum operations.

In Priv spec v1.11, RVF is v2.2. fmin.s and fmax.s are amended to
implement IEEE 754-2019 minimumNumber and maximumNumber operations.

Therefore, to prevent the risk of having too many version variables.
Instead of introducing an extra *fext_ver* variable, we tie RVF version
to Priv version. Though it's not completely accurate but is close enough.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211021160847.2748577-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6450ce5634a57e57ee8bb790c080fc7636678f3d
      
https://github.com/qemu/qemu/commit/6450ce5634a57e57ee8bb790c080fc7636678f3d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-29 (Fri, 29 Oct 2021)

  Changed paths:
    M fpu/softfloat-parts.c.inc
    M fpu/softfloat.c
    M hw/riscv/boot.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c
    M include/fpu/softfloat.h
    M include/hw/riscv/boot.h
    M include/hw/riscv/microchip_pfsoc.h
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/virt.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/fpu_helper.c
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/machine.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair23/tags/pull-riscv-to-apply-20211029-1' into staging

Fifth RISC-V PR for QEMU 6.2

 - Use a shared PLIC config helper function
 - Fixup the OpenTitan PLIC configuration
 - Add support for the experimental J extension
 - Update the fmin/fmax handling
 - Fixup VS interrupt forwarding

# gpg: Signature made Fri 29 Oct 2021 12:03:47 AM PDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]

* remotes/alistair23/tags/pull-riscv-to-apply-20211029-1:
  target/riscv: change the api for RVF/RVD fmin/fmax
  softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
  target/riscv: remove force HS exception
  target/riscv: fix VS interrupts forwarding to HS
  target/riscv: Allow experimental J-ext to be turned on
  target/riscv: Implement address masking functions required for RISC-V Pointer 
Masking extension
  target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of 
instructions
  target/riscv: Print new PM CSRs in QEMU logs
  target/riscv: Add J extension state description
  target/riscv: Support CSRs required for RISC-V PM extension except for the 
h-mode
  target/riscv: Add CSR defines for RISC-V PM extension
  target/riscv: Add J-extension into RISC-V
  hw/riscv: opentitan: Fixup the PLIC context addresses
  hw/riscv: virt: Use the PLIC config helper function
  hw/riscv: microchip_pfsoc: Use the PLIC config helper function
  hw/riscv: sifive_u: Use the PLIC config helper function
  hw/riscv: boot: Add a PLIC config string function
  hw/riscv: virt: Don't use a macro for the PLIC configuration

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/a92cecba2791...6450ce5634a5



reply via email to

[Prev in Thread] Current Thread [Next in Thread]