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[Qemu-commits] [qemu/qemu] c672f1: target/riscv: Pass the same value to
From: |
Richard Henderson |
Subject: |
[Qemu-commits] [qemu/qemu] c672f1: target/riscv: Pass the same value to oprsz and max... |
Date: |
Fri, 22 Oct 2021 12:14:54 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: c672f19f328922eff4963b0b61fbdcfa661e1c06
https://github.com/qemu/qemu/commit/c672f19f328922eff4963b0b61fbdcfa661e1c06
Author: Frank Chang <frank.chang@sifive.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
oprsz and maxsz are passed with the same value in commit: eee2d61e202.
However, vmv.v.v was missed in that commit and should pass the same
value as well in its tcg_gen_gvec_2_ptr() call.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211007081803.1705656-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e573a7f325e4d66d1005f7bb80d51ce95f307951
https://github.com/qemu/qemu/commit/e573a7f325e4d66d1005f7bb80d51ce95f307951
Author: Travis Geiselbrecht <travisg@gmail.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: line up all of the registers in the info register dump
Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.
Signed-off-by: Travis Geiselbrecht <travisg@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211009055019.545153-1-travisg@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 54c17609372bb119575f3bb7309ea57fc1a58d1d
https://github.com/qemu/qemu/commit/54c17609372bb119575f3bb7309ea57fc1a58d1d
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/insn_trans/trans_rvb.c.inc
Log Message:
-----------
target/riscv: Fix orc.b implementation
The earlier implementation fell into a corner case for bytes that were
0x01, giving a wrong result (but not affecting our application test
cases for strings, as an ASCII value 0x01 is rare in those...).
This changes the algorithm to:
1. Mask out the high-bit of each bytes (so that each byte is <= 127).
2. Add 127 to each byte (i.e. if the low 7 bits are not 0, this will overflow
into the highest bit of each byte).
3. Bitwise-or the original value back in (to cover those cases where the
source byte was exactly 128) to saturate the high-bit.
4. Shift-and-mask (implemented as a mask-and-shift) to extract the MSB of
each byte into its LSB.
5. Multiply with 0xff to fan out the LSB to all bits of each byte.
Fixes: d7a4fcb034 ("target/riscv: Add orc.b instruction for Zbb, removing
gorc/gorci")
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reported-by: Vincent Palatin <vpalatin@rivosinc.com>
Tested-by: Vincent Palatin <vpalatin@rivosinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211013184125.2010897-1-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 03fd0c5fe98f5617076527e9783d030294b64d6d
https://github.com/qemu/qemu/commit/03fd0c5fe98f5617076527e9783d030294b64d6d
Author: Mingwang Li <limingwang@huawei.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Use machine->ram as the system memory
If default main_mem is used to be registered as the system memory,
other memory cannot be initialized. Therefore, the system memory
should be initialized to the machine->ram, which consists of the
default main_mem and other possible memory required by applications,
such as shared hugepage memory in DPDK.
Also, the mc->defaul_ram_id should be set to the default main_mem,
such as "riscv_virt_board.ram" for the virt machine.
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211016030908.40480-1-limingwang@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 61d56494884b0d4bbf78d0561258b3548dea3390
https://github.com/qemu/qemu/commit/61d56494884b0d4bbf78d0561258b3548dea3390
Author: Frank Chang <frank.chang@sifive.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/cpu.h
M target/riscv/translate.c
Log Message:
-----------
target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211015074627.3957162-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 31dbcff713aa297033a008b5188fbb37abf85f36
https://github.com/qemu/qemu/commit/31dbcff713aa297033a008b5188fbb37abf85f36
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/cpu_bits.h
Log Message:
-----------
target/riscv: Remove some unused macros
Since commit 1a9540d1f1a
("target/riscv: Drop support for ISA spec version 1.09.1")
these definitions are unused, remove them.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
f4d8a7a035f39c0a35d44c1e371c5c99cc2fa15a.1634531504.git.alistair.francis@wdc.com
Commit: 9d3d60b704f48217cf9b38b883cc15c40f76f286
https://github.com/qemu/qemu/commit/9d3d60b704f48217cf9b38b883cc15c40f76f286
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Organise the CPU properties
Organise the CPU properties so that standard extensions come first
then followed by experimental extensions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alistair.francis@wdc.com
Commit: 53677acf25afa8e529d7f81a6ae9a03d15c72713
https://github.com/qemu/qemu/commit/53677acf25afa8e529d7f81a6ae9a03d15c72713
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Move cpu_get_tb_cpu_state out of line
Move the function to cpu_helper.c, as it is large and growing.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-2-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 99bc874fb3a0709c36ae4e594a1262ce1660e698
https://github.com/qemu/qemu/commit/99bc874fb3a0709c36ae4e594a1262ce1660e698
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/cpu_bits.h
Log Message:
-----------
target/riscv: Create RISCVMXL enumeration
Move the MXL_RV* defines to enumerators.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-3-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e91a7227cb802ea62ffa14707ebc2f588b01213d
https://github.com/qemu/qemu/commit/e91a7227cb802ea62ffa14707ebc2f588b01213d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M linux-user/elfload.c
M linux-user/riscv/cpu_loop.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/gdbstub.c
M target/riscv/machine.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Split misa.mxl and misa.ext
The hw representation of misa.mxl is at the high bits of the
misa csr. Representing this in the same way inside QEMU
results in overly complex code trying to check that field.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: db23e5d981ab22da0bfe1150f4828d08484b1fba
https://github.com/qemu/qemu/commit/db23e5d981ab22da0bfe1150f4828d08484b1fba
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/riscv/boot.c
M semihosting/arm-compat-semi.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/gdbstub.c
M target/riscv/monitor.c
Log Message:
-----------
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.
Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 92371bd9033e5a50a7541d96ff8ad067930a4f93
https://github.com/qemu/qemu/commit/92371bd9033e5a50a7541d96ff8ad067930a4f93
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add MXL/SXL/UXL to TB_FLAGS
Begin adding support for switching XLEN at runtime. Extract the
effective XLEN from MISA and MSTATUS and store for use during translation.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-6-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fbb48032e46976cfc94a90a4233a2060fdc36a4e
https://github.com/qemu/qemu/commit/fbb48032e46976cfc94a90a4233a2060fdc36a4e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Use REQUIRE_64BIT in amo_check64
Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-7-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4e97d459a0f2b92815c2c2c6eb96b75e2235b42e
https://github.com/qemu/qemu/commit/4e97d459a0f2b92815c2c2c6eb96b75e2235b42e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Properly check SEW in amo_op
We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less. Use a switch and explicitly
bound both SEW and SEQ for all cases.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-8-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 905b9fcde1fb84d718d95369c5d886bc81bbdd8e
https://github.com/qemu/qemu/commit/905b9fcde1fb84d718d95369c5d886bc81bbdd8e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Replace is_32bit with get_xl/get_xlen
In preparation for RV128, replace a simple predicate
with a more versatile test.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-9-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7667cafd5a0d173d1853b4d8414d4a98df1374dc
https://github.com/qemu/qemu/commit/7667cafd5a0d173d1853b4d8414d4a98df1374dc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvm.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Replace DisasContext.w with DisasContext.ol
In preparation for RV128, consider more than just "w" for
operand size modification. This will be used for the "d"
insns from RV128 as well.
Rename oper_len to get_olen to better match get_xlen.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-10-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 80347ae9f26dfafbd358d7d8d9ad175a2a624365
https://github.com/qemu/qemu/commit/80347ae9f26dfafbd358d7d8d9ad175a2a624365
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/insn_trans/trans_rvm.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Use gen_arith_per_ol for RVM
The multiply high-part instructions require a separate
implementation for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-11-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 673be37163cb44d2e1699503ccd065e9d13d4db7
https://github.com/qemu/qemu/commit/673be37163cb44d2e1699503ccd065e9d13d4db7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/insn_trans/trans_rvb.c.inc
Log Message:
-----------
target/riscv: Adjust trans_rev8_32 for riscv64
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-12-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fdab665f6e9d0919bbbab88b16ae2c4be1bf61c6
https://github.com/qemu/qemu/commit/fdab665f6e9d0919bbbab88b16ae2c4be1bf61c6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Use gen_unary_per_ol for RVB
The count zeros instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-13-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a0245d91dd1ca33ecde8c430ac6986dbd90a84db
https://github.com/qemu/qemu/commit/a0245d91dd1ca33ecde8c430ac6986dbd90a84db
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Use gen_shift*_per_ol for RVB, RVI
Most shift instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-14-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 665b90d8a4aa7d90bbeee9ff279e37edcd573635
https://github.com/qemu/qemu/commit/665b90d8a4aa7d90bbeee9ff279e37edcd573635
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Use riscv_csrrw_debug for cpu_dump
Use the official debug read interface to the csrs,
rather than referencing the env slots directly.
Put the list of csrs to dump into a table.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-15-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b550f89457ef5022231f8255ae1a6ba496c492b1
https://github.com/qemu/qemu/commit/b550f89457ef5022231f8255ae1a6ba496c492b1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Compute mstatus.sd on demand
The position of this read-only field is dependent on the current xlen.
Rather than having to compute that difference in many places, compute
it only on read.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-16-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ef6310064820183cce7c5969cae293e680c57679
https://github.com/qemu/qemu/commit/ef6310064820183cce7c5969cae293e680c57679
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/riscv/opentitan.c
M include/hw/riscv/opentitan.h
Log Message:
-----------
hw/riscv: opentitan: Update to the latest build
Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
Commit: 434e7e0217d73c20f60bd52437d0a0ba8a3c6247
https://github.com/qemu/qemu/commit/434e7e0217d73c20f60bd52437d0a0ba8a3c6247
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
R hw/intc/ibex_plic.c
M hw/intc/meson.build
Log Message:
-----------
hw/intc: Remove the Ibex PLIC
The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and
instead use the SiFive PLIC.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
Commit: d8c6590f183cd93956b7a458d212778a143b89c8
https://github.com/qemu/qemu/commit/d8c6590f183cd93956b7a458d212778a143b89c8
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/intc/sifive_plic.c
Log Message:
-----------
hw/intc: sifive_plic: Move the properties
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
3c125e27c49a4969df82bf8b197535ccd1996939.1634524691.git.alistair.francis@wdc.com
Commit: d680ff664e1c7e097922f62fef824027b8fb711a
https://github.com/qemu/qemu/commit/d680ff664e1c7e097922f62fef824027b8fb711a
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/intc/sifive_plic.c
Log Message:
-----------
hw/intc: sifive_plic: Cleanup the realize function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alistair.francis@wdc.com
Commit: 8d3dae162e61e6c71bbd3d9878cd1768ae9dd989
https://github.com/qemu/qemu/commit/8d3dae162e61e6c71bbd3d9878cd1768ae9dd989
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/intc/sifive_plic.c
Log Message:
-----------
hw/intc: sifive_plic: Cleanup the irq_request function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alistair.francis@wdc.com
Commit: d4c624f482778cfe91938996a588df2df0e70f20
https://github.com/qemu/qemu/commit/d4c624f482778cfe91938996a588df2df0e70f20
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/riscv/microchip_pfsoc.c
Log Message:
-----------
hw/riscv: microchip_pfsoc: Use MachineState::ram and
MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 91b1fbdc0cca11ac23ddc61ee3ea0e9706b645cf
https://github.com/qemu/qemu/commit/91b1fbdc0cca11ac23ddc61ee3ea0e9706b645cf
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/riscv/opentitan.c
Log Message:
-----------
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
While at it add check for user supplied RAM size and error out if it
mismatches board expected value.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 56917307f4780535d319dedc8973361a5da76f7b
https://github.com/qemu/qemu/commit/56917307f4780535d319dedc8973361a5da76f7b
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/riscv/shakti_c.c
Log Message:
-----------
hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-4-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e2b3ef75445fc2342b00680dad7af3618dc69deb
https://github.com/qemu/qemu/commit/e2b3ef75445fc2342b00680dad7af3618dc69deb
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/riscv/sifive_e.c
Log Message:
-----------
hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
While at it add check for user supplied RAM size and error out if it
mismatches board expected value.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-5-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c188a9c4f78e21f7f979ab7ef19c5bf21e9dcf08
https://github.com/qemu/qemu/commit/c188a9c4f78e21f7f979ab7ef19c5bf21e9dcf08
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/riscv/sifive_u.c
Log Message:
-----------
hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-6-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 11ec06f9eaedc801ded34c79861367b76ab2b731
https://github.com/qemu/qemu/commit/11ec06f9eaedc801ded34c79861367b76ab2b731
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
M hw/riscv/spike.c
Log Message:
-----------
hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-7-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 660efed8b37aedec9b5fcc555da1f88f7d12c98a
https://github.com/qemu/qemu/commit/660efed8b37aedec9b5fcc555da1f88f7d12c98a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-22 (Fri, 22 Oct 2021)
Changed paths:
R hw/intc/ibex_plic.c
M hw/intc/meson.build
M hw/intc/sifive_plic.c
M hw/riscv/boot.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
M hw/riscv/shakti_c.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/opentitan.h
M linux-user/elfload.c
M linux-user/riscv/cpu_loop.c
M semihosting/arm-compat-semi.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/gdbstub.c
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvm.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/machine.c
M target/riscv/monitor.c
M target/riscv/translate.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/alistair23/tags/pull-riscv-to-apply-20211022-2' into staging
Fourth RISC-V PR for QEMU 6.2
- Vector extension bug fixes
- Bit manipulation extension bug fix
- Support vhost-user and numa mem options on all boards
- Rationalise XLEN and operand lengths
- Bump the OpenTitan FPGA support
- Remove the Ibex PLIC
- General code cleanup
# gpg: Signature made Fri 22 Oct 2021 06:36:10 AM PDT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
* remotes/alistair23/tags/pull-riscv-to-apply-20211022-2: (33 commits)
hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
hw/riscv: microchip_pfsoc: Use MachineState::ram and
MachineClass::default_ram_id
hw/intc: sifive_plic: Cleanup the irq_request function
hw/intc: sifive_plic: Cleanup the realize function
hw/intc: sifive_plic: Move the properties
hw/intc: Remove the Ibex PLIC
hw/riscv: opentitan: Update to the latest build
target/riscv: Compute mstatus.sd on demand
target/riscv: Use riscv_csrrw_debug for cpu_dump
target/riscv: Use gen_shift*_per_ol for RVB, RVI
target/riscv: Use gen_unary_per_ol for RVB
target/riscv: Adjust trans_rev8_32 for riscv64
target/riscv: Use gen_arith_per_ol for RVM
target/riscv: Replace DisasContext.w with DisasContext.ol
target/riscv: Replace is_32bit with get_xl/get_xlen
target/riscv: Properly check SEW in amo_op
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/2c64ff92ecef...660efed8b37a
- [Qemu-commits] [qemu/qemu] c672f1: target/riscv: Pass the same value to oprsz and max...,
Richard Henderson <=