[Qemu-commits] [qemu/qemu] 37eadc: hw: arm: aspeed: Enable eth0 interface for aspeed-...

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 37eadc25ea316e9b722d9a82b3fe9e25ab83ddb3
      
https://github.com/qemu/qemu/commit/37eadc25ea316e9b722d9a82b3fe9e25ab83ddb3
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb

Commit 7582591ae7 ("aspeed: Support AST2600A1 silicon revision") switched
the silicon revision for AST2600 to revision A1. On revision A1, the first
Ethernet interface is operational. Enable it.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210808200457.889955-1-linux@roeck-us.net>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: b2f5e4862cbc5f9126b0e7e8717916d1b9af8cfb
      
https://github.com/qemu/qemu/commit/b2f5e4862cbc5f9126b0e7e8717916d1b9af8cfb
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  hw: arm: aspeed: Enable mac0/1 instead of mac1/2 for g220a

According to its dts file in the Linux kernel, we need mac0 and mac1 enabled
instead of mac1 and mac2. Also, g220a is based on aspeed-g5 (ast2500) which
doesn't even have the third interface.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210810035742.550391-1-linux@roeck-us.net>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 2b92f599b135f129ce5d41a8cdf99a480084ff0a
      
https://github.com/qemu/qemu/commit/2b92f599b135f129ce5d41a8cdf99a480084ff0a
  Author: Andrew Jeffery <andrew@aj.id.au>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/watchdog/wdt_aspeed.c
    M include/hw/watchdog/wdt_aspeed.h

  Log Message:
  -----------
  watchdog: aspeed: Sanitize control register values

While some of the critical fields remain the same, there is variation in
the definition of the control register across the SoC generations.
Reserved regions are adjusted, while in other cases the mutability or
behaviour of fields change.

Introduce a callback to sanitize the value on writes to ensure model
behaviour reflects the hardware.

Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210709053107.1829304-2-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: b2884e99d75e32733ed4d7bb03a7408839a91079
      
https://github.com/qemu/qemu/commit/b2884e99d75e32733ed4d7bb03a7408839a91079
  Author: Andrew Jeffery <andrew@aj.id.au>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/watchdog/wdt_aspeed.c

  Log Message:
  -----------
  watchdog: aspeed: Fix sequential control writes

The logic in the handling for the control register required toggling the
enable state for writes to stick. Rework the condition chain to allow
sequential writes that do not update the enable state.

Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210709053107.1829304-3-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 879609d49516cd46a4dc0b2d2cef6b5b5b8c2a3b
      
https://github.com/qemu/qemu/commit/879609d49516cd46a4dc0b2d2cef6b5b5b8c2a3b
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/gpio/aspeed_gpio.c

  Log Message:
  -----------
  hw: aspeed_gpio: Simplify 1.8V defines

There's no need to define the registers relative to the 0x800 offset
where the controller is mapped, as the device is instantiated as it's
own model at the correct memory address.

Simplify the defines and remove the offset to save future confusion.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210713065854.134634-3-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 0810abd3e4da3ce425bc110fa40722c6575ce981
      
https://github.com/qemu/qemu/commit/0810abd3e4da3ce425bc110fa40722c6575ce981
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/gpio/aspeed_gpio.c

  Log Message:
  -----------
  hw: aspeed_gpio: Clarify GPIO controller name

There are two GPIO controllers in the ast2600; one is 3.3V and the other
is 1.8V.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210713065854.134634-4-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 70e58a7d453a786db6f7c61632f2ab2f60cafc3e
      
https://github.com/qemu/qemu/commit/70e58a7d453a786db6f7c61632f2ab2f60cafc3e
  Author: Andrew Jeffery <andrew@aj.id.au>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/misc/pca9552.c

  Log Message:
  -----------
  misc/pca9552: Fix LED status register indexing in pca955x_get_led()

There was a bit of a thinko in the state calculation where every odd pin
in was reported in e.g. "pwm0" mode rather than "off". This was the
result of an incorrect bit shift for the 2-bit field representing each
LED state.

Fixes: a90d8f84674d ("misc/pca9552: Add qom set and get")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210723043624.348158-1-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 91621b2feb90a47bd6c20a7b99b3c9976c1baab1
      
https://github.com/qemu/qemu/commit/91621b2feb90a47bd6c20a7b99b3c9976c1baab1
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  arm/aspeed: rainier: Add i2c eeproms and muxes

These are the devices documented by the Rainier device tree. With this
we can see the guest discovering the multiplexers and probing the eeprom
devices:

 i2c i2c-2: Added multiplexed i2c bus 16
 i2c i2c-2: Added multiplexed i2c bus 17
 i2c i2c-2: Added multiplexed i2c bus 18
 i2c i2c-2: Added multiplexed i2c bus 19
 i2c-mux-gpio i2cmux: 4 port mux on 1e78a180.i2c-bus adapter
 at24 20-0050: 8192 byte 24c64 EEPROM, writable, 1 bytes/write
 i2c i2c-4: Added multiplexed i2c bus 20
 at24 21-0051: 8192 byte 24c64 EEPROM, writable, 1 bytes/write
 i2c i2c-4: Added multiplexed i2c bus 21
 at24 22-0052: 8192 byte 24c64 EEPROM, writable, 1 bytes/write

Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: Introduced aspeed_eeprom_init ]
Message-Id: <20210629142336.750058-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: fc7dbc8d3e7867d294ae97e3f18ffc8bdf3587bc
      
https://github.com/qemu/qemu/commit/fc7dbc8d3e7867d294ae97e3f18ffc8bdf3587bc
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/aspeed_ast2600.c
    M hw/misc/aspeed_scu.c
    M include/hw/misc/aspeed_scu.h

  Log Message:
  -----------
  aspeed: Emulate the AST2600A3

This is the latest revision of the ASPEED 2600 SoC. As there is no
need to model multiple revisions of the same SoC for the moment,
update the SCU AST2600 to model the A3 revision instead of the A1 and
adapt the AST2600 SoC and machines.

Reset values are taken from v8 of the datasheet.

Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: - Introduced an Aspeed "ast2600-a3" SoC class
       - Commit log update ]
Message-Id: <20210629142336.750058-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 836807c66f01002fc082b1f9a7bacb27d5803e31
      
https://github.com/qemu/qemu/commit/836807c66f01002fc082b1f9a7bacb27d5803e31
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/Kconfig
    M hw/sensor/Kconfig
    A hw/sensor/dps310.c
    M hw/sensor/meson.build

  Log Message:
  -----------
  hw/misc: Add Infineon DPS310 sensor model

This contains some hardcoded register values that were obtained from the
hardware after reading the temperature.

It does enough to test the Linux kernel driver. The FIFO mode, IRQs and
operation modes other than the default as used by Linux are not modelled.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20210616073358.750472-2-joel@jms.id.au>
[ clg: - Fixed sequential reading
       - Reworked regs_reset_state array
       - Moved model under hw/sensor/ ]
Message-Id: <20210629142336.750058-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 9b3e198a79ea9de809031d97d17a880355b8dd0f
      
https://github.com/qemu/qemu/commit/9b3e198a79ea9de809031d97d17a880355b8dd0f
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  arm/aspeed: Add DPS310 to Witherspoon and Rainier

Witherspoon uses the DPS310 as a temperature sensor. Rainier uses it as
a temperature and humidity sensor.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210629142336.750058-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 93baa424b57433a981dfe9be7f3a07a7c6f27b1e
      
https://github.com/qemu/qemu/commit/93baa424b57433a981dfe9be7f3a07a7c6f27b1e
  Author: Peter Delevoryas <pdel@fb.com>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/misc/aspeed_scu.c

  Log Message:
  -----------
  hw/arm/aspeed: Initialize AST2600 UART clock selection registers

UART5 is typically used as the default debug UART on the AST2600, but
UART1 is also designed to be a debug UART. All the AST2600 UART's have
semi-configurable clock rates through registers in the System Control
Unit (SCU), but only UART5 works out of the box with zero-initialized
values. The rest of the UART's expect a few of the registers to be
initialized to non-zero values, or else the clock rate calculation will
yield zero or undefined (due to a divide-by-zero).

For reference, the U-Boot clock rate driver here shows the calculation:

    
https://github.com/facebook/openbmc-uboot/blob/15f7e0dc01d8/drivers/clk/aspeed/clk_ast2600.c#L357

To summarize, UART5 allows selection from 4 rates: 24 MHz, 192 MHz, 24 /
13 MHz, and 192 / 13 MHz. The other UART's allow selecting either the
"low" rate (UARTCLK) or the "high" rate (HUARTCLK). UARTCLK and HUARTCLK
are configurable themselves:

    UARTCLK = UXCLK * R / (N * 2)
    HUARTCLK = HUXCLK * HR / (HN * 2)

UXCLK and HUXCLK are also configurable, and depend on the APLL and/or
HPLL clock rates, which also derive from complicated calculations. Long
story short, there's lots of multiplication and division from
configurable registers, and most of these registers are zero-initialized
in QEMU, which at best is unexpected and at worst causes this clock rate
driver to hang from divide-by-zero's. This can also be difficult to
diagnose, because it may cause U-Boot to hang before serial console
initialization completes, requiring intervention from gdb.

This change just initializes all of these registers with default values
from the datasheet.

To test this, I used Facebook's AST2600 OpenBMC image for "fuji", with
the following diff applied (because fuji uses UART1 for console output,
not UART5).

  @@ -323,8 +323,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, 
Error **errp)
       }

      /* UART - attach an 8250 to the IO space as our UART5 */
  -    serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
  -                   aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
  +    serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART1], 2,
  +                   aspeed_soc_get_irq(s, ASPEED_DEV_UART1),
                    38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);

       /* I2C */

Without these clock rate registers being initialized, U-Boot hangs in
the clock rate driver from a divide-by-zero, because the UART1 clock
rate register reads return zero, and there's no console output. After
initializing them with default values, fuji boots successfully.

Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[ clg: Removed _PARAM suffix ]
Message-Id: <20210906134023.3711031-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: a2b45c65baaed6675c6f612c5dc4e7c0f597a757
      
https://github.com/qemu/qemu/commit/a2b45c65baaed6675c6f612c5dc4e7c0f597a757
  Author: Peter Delevoryas <pdel@fb.com>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed.h
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  hw/arm/aspeed: Allow machine to set UART default

When you run QEMU with an Aspeed machine and a single serial device
using stdio like this:

    qemu -machine ast2600-evb -drive ... -serial stdio

The guest OS can read and write to the UART5 registers at 0x1E784000 and
it will receive from stdin and write to stdout. The Aspeed SoC's have a
lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on
the board design, may be using any of them as the serial console. (See
"stdout-path" in a DTS to check which one is chosen).

Most boards, including all of those currently defined in
hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds
some flexibility for different boards without requiring users to change
their command-line invocation of QEMU.

I tested this doesn't break existing code by booting an AST2500 OpenBMC
image and an AST2600 OpenBMC image, each using UART5 as the console.

Then I tested switching the default to UART1 and booting an AST2600
OpenBMC image that uses UART1, and that worked too.

Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210901153615.2746885-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: d7add12e20fa8982f5932ff4dca317c5d2dfe7d9
      
https://github.com/qemu/qemu/commit/d7add12e20fa8982f5932ff4dca317c5d2dfe7d9
  Author: Peter Delevoryas <pdel@fb.com>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  hw/arm/aspeed: Add Fuji machine type

This adds a new machine type "fuji-bmc" based on the following device tree:

https://github.com/torvalds/linux/blob/40cb6373b46/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts

Most of the i2c devices are not there, they're added here:

https://github.com/facebook/openbmc/blob/fb2ed12002fb/meta-facebook/meta-fuji/recipes-utils/openbmc-utils/files/setup_i2c.sh

I tested this by building a Fuji image from Facebook's OpenBMC repo,
booting, and ssh'ing from host-to-guest.

Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20210906133124.3674661-1-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 8db7d88dd4453c88d6bd7abf9b9580e818bb0912
      
https://github.com/qemu/qemu/commit/8db7d88dd4453c88d6bd7abf9b9580e818bb0912
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M hw/arm/Kconfig
    M hw/arm/aspeed.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    M hw/gpio/aspeed_gpio.c
    M hw/misc/aspeed_scu.c
    M hw/misc/pca9552.c
    M hw/sensor/Kconfig
    A hw/sensor/dps310.c
    M hw/sensor/meson.build
    M hw/watchdog/wdt_aspeed.c
    M include/hw/arm/aspeed.h
    M include/hw/arm/aspeed_soc.h
    M include/hw/misc/aspeed_scu.h
    M include/hw/watchdog/wdt_aspeed.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210913' 
into staging

Aspeed patches :

* MAC enablement fixes (Guenter)
* Watchdog  and pca9552 fixes (Andrew)
* GPIO fixes (Joel)
* AST2600A3 SoC and DPS310 models (Joel)
* New Fuji BMC machine (Peter)

# gpg: Signature made Mon 13 Sep 2021 14:19:51 BST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* remotes/legoater/tags/pull-aspeed-20210913:
  hw/arm/aspeed: Add Fuji machine type
  hw/arm/aspeed: Allow machine to set UART default
  hw/arm/aspeed: Initialize AST2600 UART clock selection registers
  arm/aspeed: Add DPS310 to Witherspoon and Rainier
  hw/misc: Add Infineon DPS310 sensor model
  aspeed: Emulate the AST2600A3
  arm/aspeed: rainier: Add i2c eeproms and muxes
  misc/pca9552: Fix LED status register indexing in pca955x_get_led()
  hw: aspeed_gpio: Clarify GPIO controller name
  hw: aspeed_gpio: Simplify 1.8V defines
  watchdog: aspeed: Fix sequential control writes
  watchdog: aspeed: Sanitize control register values
  hw: arm: aspeed: Enable mac0/1 instead of mac1/2 for g220a
  hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/c6f5e042d89e...8db7d88dd445