[Qemu-commits] [qemu/qemu] b53281: target/sparc: Drop use of gen_io_end()

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: b5328172a94b223da742dc73555469b6418535ab
      
https://github.com/qemu/qemu/commit/b5328172a94b223da742dc73555469b6418535ab
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Drop use of gen_io_end()

The gen_io_end() function is obsolete (as documented in
docs/devel/tcg-icount.rst). Where an instruction is an I/O
operation, the translator frontend should call gen_io_start()
before generating the code which does the I/O, and then
end the TB immediately after this insn.

Remove the calls to gen_io_end() in the SPARC frontend,
and ensure that the insns which were calling it end the
TB if they didn't do so already.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210724134902.7785-2-peter.maydell@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: f383eb80f6823663b9b440f779083063ef55aec0
      
https://github.com/qemu/qemu/commit/f383eb80f6823663b9b440f779083063ef55aec0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M docs/devel/tcg-icount.rst
    M include/exec/gen-icount.h

  Log Message:
  -----------
  tcg: Drop gen_io_end()

Now we have removed all the uses of gen_io_end() from target frontends,
the only callsite is inside gen_tb_start(). Inline the code there,
and remove the reference to it from the documentation.

While we are inlining the code, switch it to use tcg_constant_i32()
so we don't have to manually create and destroy a TCG temporary.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210724134902.7785-3-peter.maydell@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: e97a8a5926968a1028902318d2f396c4bfc5755b
      
https://github.com/qemu/qemu/commit/e97a8a5926968a1028902318d2f396c4bfc5755b
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M hw/sparc/sun4m.c

  Log Message:
  -----------
  sun4m: fix setting CPU id when more than one CPU is present

Commit 24f675cd3b ("sparc/sun4m: Use start-powered-off CPUState property") 
changed
the sun4m CPU reset code to use the start-powered-off property and so split the
creation of the CPU into separate instantiation and realization phases to enable
the new start-powered-off property to be set.

This accidentally broke sun4m machines with more than one CPU present since
sparc_cpu_realizefn() sets a default CPU id, and now that realization occurs 
after
calling cpu_sparc_set_id() in cpu_devinit() the CPU id gets reset back to the
default instead of being uniquely encoded based upon the CPU number. As soon as
another CPU is brought online, the OS gets confused between them and promptly
panics.

Resolve the issue by moving the cpu_sparc_set_id() call in cpu_devinit() to 
after
the point where the CPU device has been realized as before.

Fixes: 24f675cd3b ("sparc/sun4m: Use start-powered-off CPUState property")
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210825095100.20180-1-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 0e042025b9fe262316f29e4b8ec47f0b85c24e5f
      
https://github.com/qemu/qemu/commit/0e042025b9fe262316f29e4b8ec47f0b85c24e5f
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M hw/char/escc.c

  Log Message:
  -----------
  escc: checkpatch fixes

Also fix a couple of spelling mistakes in comments.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 9d248a4be524a6c820634e9b58e79085972cb78f
      
https://github.com/qemu/qemu/commit/9d248a4be524a6c820634e9b58e79085972cb78f
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M hw/char/escc.c

  Log Message:
  -----------
  escc: reset register values to zero in escc_reset()

This is to ensure that a device reset always returns the ESCC to a known state.

Note that this is currently redundant with the same code in escc_reset_chn()
but that will change shortly.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 8e8aa96590156577ed8a2623d1a2e4db4e5748b8
      
https://github.com/qemu/qemu/commit/8e8aa96590156577ed8a2623d1a2e4db4e5748b8
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M hw/char/escc.c
    M hw/char/trace-events

  Log Message:
  -----------
  escc: introduce escc_soft_reset_chn() for software reset

This new software reset function is to be called when the appropriate channel
software reset bit is written to register WR9. Its initial implementation is
the same as the existing escc_reset_chn() function used for device reset.

Add a new trace event when the guest initiates a soft reset via the WR9 register
to help diagnose guest reset issues.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-4-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: bf4fbb69f36d9697a7d62d767de024fd9062d31d
      
https://github.com/qemu/qemu/commit/bf4fbb69f36d9697a7d62d767de024fd9062d31d
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M hw/char/escc.c
    M hw/char/trace-events

  Log Message:
  -----------
  escc: introduce escc_hard_reset_chn() for hardware reset

This new hardware reset function is to be called for both channels when the
hardware reset bit is written to register WR9. Its initial implementation is
the same as the existing escc_reset_chn() function used for device reset.

Add a new trace event when the guest initiates a hard reset via the WR9 register
to help diagnose guest reset issues.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-5-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 1f476e78a80b72d668f82cc7fe01cf2166f8c352
      
https://github.com/qemu/qemu/commit/1f476e78a80b72d668f82cc7fe01cf2166f8c352
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M hw/char/escc.c

  Log Message:
  -----------
  escc: implement soft reset as described in the datasheet

The software reset differs from a device reset in that it only changes the 
contents
of specific registers. Remove the code that resets all the registers to zero 
during
soft reset and implement the default values listed in the table in the "Z85C30 
Reset"
section.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-6-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 160509aebecded2051bd74d00022d052c7c769be
      
https://github.com/qemu/qemu/commit/160509aebecded2051bd74d00022d052c7c769be
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M hw/char/escc.c

  Log Message:
  -----------
  escc: implement hard reset as described in the datasheet

The hardware reset differs from a device reset in that it only changes the 
contents
of specific registers. Remove the code that resets all the registers to zero 
during
hardware reset and implement the default values using the existing soft reset 
code
with the additional changes listed in the table in the "Z85C30 Reset" section.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-7-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: a04ca92a54776d832e719252b252c69339b28ec7
      
https://github.com/qemu/qemu/commit/a04ca92a54776d832e719252b252c69339b28ec7
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M hw/char/escc.c

  Log Message:
  -----------
  escc: remove register changes from escc_reset_chn()

Now that register values at reset are handled elsewhere for all of device reset,
soft reset and hard reset, escc_reset_chn() only needs to handle initialisation
of internal device state.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-8-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 99b0f0584132d942547046bc064478db5bcbe7c5
      
https://github.com/qemu/qemu/commit/99b0f0584132d942547046bc064478db5bcbe7c5
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M hw/char/escc.c

  Log Message:
  -----------
  escc: re-use escc_reset_chn() for soft reset

This removes duplication of the internal device state initialisation between
device reset and soft reset.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-9-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 15a2a1a4d1eecc74a87e1552f5cc4e3668375715
      
https://github.com/qemu/qemu/commit/15a2a1a4d1eecc74a87e1552f5cc4e3668375715
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M hw/char/escc.c

  Log Message:
  -----------
  escc: fix STATUS_SYNC bit in R_STATUS register

After an SDLC "Enter hunt" command has been sent the STATUS_SYNC bit should 
remain
high until the flag byte has been detected. Whilst the ESCC device doesn't yet
implement SDLC mode, without this change the active low STATUS_SYNC is 
constantly
asserted causing the MacOS OpenTransport extension to hang on startup as it 
thinks
it is constantly receiving LocalTalk responses during its initial negotiation
phase.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-10-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 500f1f3e81ad112e28b7c979136847e32dad83b6
      
https://github.com/qemu/qemu/commit/500f1f3e81ad112e28b7c979136847e32dad83b6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-09 (Thu, 09 Sep 2021)

  Changed paths:
    M docs/devel/tcg-icount.rst
    M hw/char/escc.c
    M hw/char/trace-events
    M hw/sparc/sun4m.c
    M include/exec/gen-icount.h
    M target/sparc/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20210908' into 
staging

qemu-sparc queue

# gpg: Signature made Wed 08 Sep 2021 12:48:40 BST
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" 
[full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-sparc-20210908:
  escc: fix STATUS_SYNC bit in R_STATUS register
  escc: re-use escc_reset_chn() for soft reset
  escc: remove register changes from escc_reset_chn()
  escc: implement hard reset as described in the datasheet
  escc: implement soft reset as described in the datasheet
  escc: introduce escc_hard_reset_chn() for hardware reset
  escc: introduce escc_soft_reset_chn() for software reset
  escc: reset register values to zero in escc_reset()
  escc: checkpatch fixes
  sun4m: fix setting CPU id when more than one CPU is present
  tcg: Drop gen_io_end()
  target/sparc: Drop use of gen_io_end()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/7084037070bc...500f1f3e81ad