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[Qemu-commits] [qemu/qemu] 0f76de: stm32f100: Add the stm32f100 SoC
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] 0f76de: stm32f100: Add the stm32f100 SoC |
Date: |
Sun, 11 Jul 2021 06:31:54 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 0f76debd1fff9bb8234e9ca921ef6f9c14be46a9
https://github.com/qemu/qemu/commit/0f76debd1fff9bb8234e9ca921ef6f9c14be46a9
Author: Alexandre Iooss <erdnaxe@crans.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M MAINTAINERS
M hw/arm/Kconfig
M hw/arm/meson.build
A hw/arm/stm32f100_soc.c
A include/hw/arm/stm32f100_soc.h
Log Message:
-----------
stm32f100: Add the stm32f100 SoC
This SoC is similar to stm32f205 SoC.
This will be used by the STM32VLDISCOVERY to create a machine.
Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-2-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2ac2410c5e39ac4a317b38d14f0f878fe007c6e5
https://github.com/qemu/qemu/commit/2ac2410c5e39ac4a317b38d14f0f878fe007c6e5
Author: Alexandre Iooss <erdnaxe@crans.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M MAINTAINERS
M default-configs/devices/arm-softmmu.mak
M hw/arm/Kconfig
M hw/arm/meson.build
A hw/arm/stm32vldiscovery.c
Log Message:
-----------
stm32vldiscovery: Add the STM32VLDISCOVERY Machine
This is a Cortex-M3 based machine. Information can be found at:
https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-3-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1af060e57480905f91f88362f867fec8e20b566e
https://github.com/qemu/qemu/commit/1af060e57480905f91f88362f867fec8e20b566e
Author: Alexandre Iooss <erdnaxe@crans.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M MAINTAINERS
A docs/system/arm/stm32.rst
M docs/system/target-arm.rst
Log Message:
-----------
docs/system: arm: Add stm32 boards description
This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCOVERY.
Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-4-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7cb4097f2d559b5ea4ad993653abc1e542deb625
https://github.com/qemu/qemu/commit/7cb4097f2d559b5ea4ad993653abc1e542deb625
Author: Alexandre Iooss <erdnaxe@crans.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M tests/qtest/boot-serial-test.c
Log Message:
-----------
tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
New mini-kernel test for STM32VLDISCOVERY USART1.
Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-5-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f4ec71d07cd2375c9080fbd4e85beffd05d73a11
https://github.com/qemu/qemu/commit/f4ec71d07cd2375c9080fbd4e85beffd05d73a11
Author: Ricardo Koller <ricarkol@google.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
icv_eoir_write() and icv_dir_write() ignore invalid virtual IRQ numbers
(like LPIs). The issue is that these functions check against the number
of implemented IRQs (QEMU's default is num_irq=288) which can be lower
than the maximum virtual IRQ number (1020 - 1). The consequence is that
if a hypervisor creates an LR for an IRQ between 288 and 1020, then the
guest is unable to deactivate the resulting IRQ. Note that other
functions that deal with large IRQ numbers, like icv_iar_read, check
against 1020 and not against num_irq.
Fix the checks by using GICV3_MAXIRQ (1020) instead of the number of
implemented IRQs.
Signed-off-by: Ricardo Koller <ricarkol@google.com>
Message-id: 20210702233701.3369-1-ricarkol@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 102d7d1fba6d1121c86ef31c33b808a3104ab263
https://github.com/qemu/qemu/commit/102d7d1fba6d1121c86ef31c33b808a3104ab263
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/gpio/pl061.c
M hw/gpio/trace-events
Log Message:
-----------
hw/gpio/pl061: Convert DPRINTF to tracepoints
Convert the use of the DPRINTF debug macro in the PL061 model to
use tracepoints.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e24a9f6a595cc4502b67046ea3860cae2be15b71
https://github.com/qemu/qemu/commit/e24a9f6a595cc4502b67046ea3860cae2be15b71
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/gpio/pl061.c
Log Message:
-----------
hw/gpio/pl061: Clean up read/write offset handling logic
Currently the pl061_read() and pl061_write() functions handle offsets
using a combination of three if() statements and a switch(). Clean
this up to use just a switch, using case ranges.
This requires that instead of catching accesses to the luminary-only
registers on a stock PL061 via a check on s->rsvd_start we use
an "is this luminary?" check in the cases for each luminary-only
register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 74d359b52db760f8818476f4fbaab0ffab76a8ef
https://github.com/qemu/qemu/commit/74d359b52db760f8818476f4fbaab0ffab76a8ef
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/gpio/pl061.c
M hw/gpio/trace-events
Log Message:
-----------
hw/gpio/pl061: Add tracepoints for register read and write
Add tracepoints for reads and writes to the PL061 registers. This requires
restructuring pl061_read() to only return after the tracepoint, rather
than having lots of early-returns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 455736df2cfd3a980782986d597132776d630823
https://github.com/qemu/qemu/commit/455736df2cfd3a980782986d597132776d630823
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/gpio/pl061.c
Log Message:
-----------
hw/gpio/pl061: Document the interface of this device
Add a comment documenting the "QEMU interface" of this device:
which MMIO regions, IRQ lines, GPIO lines, etc it exposes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ad06d56fc7155c7893b18efecb9fe0f2e9124eaf
https://github.com/qemu/qemu/commit/ad06d56fc7155c7893b18efecb9fe0f2e9124eaf
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/gpio/pl061.c
M hw/gpio/trace-events
Log Message:
-----------
hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR
which lets the guest configure whether the GPIO lines are pull-up,
pull-down, or truly floating. Instead of assuming all lines are pulled
high, honour the PUR and PDR registers.
For the plain PL061, continue to assume that lines have an external
pull-up resistor, as we did before.
The stellaris board actually relies on this behaviour -- the CD line
of the ssd0323 display device is connected to GPIO output C7, and it
is only because of a different bug which we're about to fix that we
weren't incorrectly driving this line high on reset and putting the
ssd0323 into data mode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c1e69e92aea696fa148c4d79aff6a2fdf46ef2b8
https://github.com/qemu/qemu/commit/c1e69e92aea696fa148c4d79aff6a2fdf46ef2b8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/gpio/pl061.c
Log Message:
-----------
hw/gpio/pl061: Make pullup/pulldown of outputs configurable
The PL061 GPIO does not itself include pullup or pulldown resistors
to set the value of a GPIO line treated as an output when it is
configured as an input (ie when the PL061 itself is not driving it).
In real hardware it is up to the board to add suitable pullups or
pulldowns. Currently our implementation hardwires this to "outputs
pulled high", which is correct for some boards (eg the realview ones:
see figure 3-29 in the "RealView Platform Baseboard for ARM926EJ-S
User Guide" DUI0224I), but wrong for others.
In particular, the wiring in the 'virt' board and the gpio-pwr device
assumes that wires should be pulled low, because otherwise the
pull-to-high will trigger a shutdown or reset action. (The only
reason this doesn't happen immediately on startup is due to another
bug in the PL061, where we don't assert the GPIOs to the correct
value on reset, but will do so as soon as the guest touches a
register and pl061_update() gets called.)
Add properties to the pl061 so the board can configure whether it
wants GPIO lines to have pullup, pulldown, or neither.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d6773a1f996db5339cdc1e01f14ffb70ca9f4d28
https://github.com/qemu/qemu/commit/d6773a1f996db5339cdc1e01f14ffb70ca9f4d28
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Make PL061 GPIO lines pulled low, not high
For the virt board we have two PL061 devices -- one for NonSecure which
is inputs only, and one for Secure which is outputs only. For the former,
we don't care whether its outputs are pulled low or high when the line is
configured as an input, because we don't connect them. For the latter,
we do care, because we wire the lines up to the gpio-pwr device, which
assumes that level 1 means "do the action" and 1 means "do nothing".
For consistency in case we add more outputs in future, configure both
PL061s to pull GPIO lines down to 0.
Reported-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ef4989b0a898ae20a974d261b14d4e5c1c097292
https://github.com/qemu/qemu/commit/ef4989b0a898ae20a974d261b14d4e5c1c097292
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/gpio/pl061.c
M hw/gpio/trace-events
Log Message:
-----------
hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on
reset
The PL061 comes out of reset with all its lines configured as input,
which means they might need to be pulled to 0 or 1 depending on the
'pullups' and 'pulldowns' properties. Currently we do not assert
these lines on reset; they will only be set whenever the guest first
touches a register that triggers a call to pl061_update().
Convert the device to three-phase reset so we have a place where we
can safely call qemu_set_irq() to set the floating lines to their
correct values.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0642e159d2351a8fd7d03f78b5d97010cd514561
https://github.com/qemu/qemu/commit/0642e159d2351a8fd7d03f78b5d97010cd514561
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/gpio/pl061.c
Log Message:
-----------
hw/gpio/pl061: Document a shortcoming in our implementation
The Luminary PL061s in the Stellaris LM3S9695 don't all have the same
reset value for GPIOPUR. We can get away with not letting the board
configure the PUR reset value because we don't actually wire anything
up to the lines which should reset to pull-up. Add a comment noting
this omission.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 5092e014f4dd6a0174e487741382053694527bc5
https://github.com/qemu/qemu/commit/5092e014f4dd6a0174e487741382053694527bc5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/arm/stellaris.c
Log Message:
-----------
hw/arm/stellaris: Expand comment about handling of OLED chipselect
The stellaris board doesn't emulate the handling of the OLED
chipselect line correctly. Expand the comment describing this,
including a sketch of the theoretical correct way to do it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 49a6f3bffbdfada7d5e9ba6e272713eba19dbf12
https://github.com/qemu/qemu/commit/49a6f3bffbdfada7d5e9ba6e272713eba19dbf12
Author: hnick@vmware.com <hnick@vmware.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
Signed-off-by: Nick Hudson <hnick@vmware.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646
https://github.com/qemu/qemu/commit/05449abb1d4c5f0c69ceb3d8d03cbc75de39b646
Author: Rebecca Cran <rebecca@nuviainc.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/intc/arm_gicv3_redist.c
Log Message:
-----------
hw/intc: Improve formatting of MEMTX_ERROR guest error message
Add a space in the message printed when gicr_read*/gicr_write* returns
MEMTX_ERROR in arm_gicv3_redist.c.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210706211432.31902-1-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3cfcc329afd99138e654b65f6f49156fca2e8cdd
https://github.com/qemu/qemu/commit/3cfcc329afd99138e654b65f6f49156fca2e8cdd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-11 (Sun, 11 Jul 2021)
Changed paths:
M MAINTAINERS
M default-configs/devices/arm-softmmu.mak
A docs/system/arm/stm32.rst
M docs/system/target-arm.rst
M hw/arm/Kconfig
M hw/arm/meson.build
M hw/arm/stellaris.c
A hw/arm/stm32f100_soc.c
A hw/arm/stm32vldiscovery.c
M hw/arm/virt.c
M hw/gpio/pl061.c
M hw/gpio/trace-events
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/arm_gicv3_redist.c
A include/hw/arm/stm32f100_soc.h
M target/arm/helper.c
M tests/qtest/boot-serial-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210709'
into staging
target-arm queue:
* New machine type: stm32vldiscovery
* hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
* hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
* virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
* Correct the encoding of MDCCSR_EL0 and DBGDSCRint
* hw/intc: Improve formatting of MEMTX_ERROR guest error message
# gpg: Signature made Fri 09 Jul 2021 17:09:10 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210709:
hw/intc: Improve formatting of MEMTX_ERROR guest error message
target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
hw/arm/stellaris: Expand comment about handling of OLED chipselect
hw/gpio/pl061: Document a shortcoming in our implementation
hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on
reset
hw/arm/virt: Make PL061 GPIO lines pulled low, not high
hw/gpio/pl061: Make pullup/pulldown of outputs configurable
hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
hw/gpio/pl061: Document the interface of this device
hw/gpio/pl061: Add tracepoints for register read and write
hw/gpio/pl061: Clean up read/write offset handling logic
hw/gpio/pl061: Convert DPRINTF to tracepoints
hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
docs/system: arm: Add stm32 boards description
stm32vldiscovery: Add the STM32VLDISCOVERY Machine
stm32f100: Add the stm32f100 SoC
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/42e1d798a6a0...3cfcc329afd9