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[Qemu-commits] [qemu/qemu] 283fc5: target/arm: Implement an IMPDEF pauth
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 283fc5: target/arm: Implement an IMPDEF pauth algorithm |
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Date: |
Tue, 19 Jan 2021 08:33:43 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 283fc52ade85eb50141f3b8b85f82b07d016cb17
https://github.com/qemu/qemu/commit/283fc52ade85eb50141f3b8b85f82b07d016cb17
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M include/qemu/xxhash.h
M target/arm/cpu.h
M target/arm/pauth_helper.c
Log Message:
-----------
target/arm: Implement an IMPDEF pauth algorithm
Without hardware acceleration, a cryptographically strong
algorithm is too expensive for pauth_computepac.
Even with hardware accel, we are not currently expecting
to link the linux-user binaries to any crypto libraries,
and doing so would generally make the --static build fail.
So choose XXH64 as a reasonably quick and decent hash.
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210111235740.462469-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: eb94284d0812b4e7c11c5d075b584100ac1c1b9a
https://github.com/qemu/qemu/commit/eb94284d0812b4e7c11c5d075b584100ac1c1b9a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M docs/system/arm/cpu-features.rst
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/monitor.c
M tests/qtest/arm-cpu-features.c
Log Message:
-----------
target/arm: Add cpu properties to control pauth
The crypto overhead of emulating pauth can be significant for
some workloads. Add two boolean properties that allows the
feature to be turned off, on with the architected algorithm,
or on with an implementation defined algorithm.
We need two intermediate booleans to control the state while
parsing properties lest we clobber ID_AA64ISAR1 into an invalid
intermediate state.
Tested-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210111235740.462469-3-richard.henderson@linaro.org
[PMM: fixed docs typo, tweaked text to clarify that the impdef
algorithm is specific to QEMU]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8073b871870538dc472e7a7f95cb8b53e81485b1
https://github.com/qemu/qemu/commit/8073b871870538dc472e7a7f95cb8b53e81485b1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Use object_property_add_bool for "sve" property
The interface for object_property_add_bool is simpler,
making the code easier to understand.
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210111235740.462469-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cc974d5cd84ea60a3dad59752aea712f3d47f8ce
https://github.com/qemu/qemu/commit/cc974d5cd84ea60a3dad59752aea712f3d47f8ce
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/cpu.c
M target/arm/helper.c
Log Message:
-----------
target/arm: remove redundant tests
In this context, the HCR value is the effective value, and thus is
zero in secure mode. The tests for HCR.{F,I}MO are sufficient.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-1-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f3ee5160ce3c03795a28e16d1a0b4916a6c959f4
https://github.com/qemu/qemu/commit/f3ee5160ce3c03795a28e16d1a0b4916a6c959f4
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: add arm_is_el2_enabled() helper
This checks if EL2 is enabled (meaning EL2 registers take effects) in
the current security context.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-2-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e6ef0169264b00cce552404f689ce137018ff290
https://github.com/qemu/qemu/commit/e6ef0169264b00cce552404f689ce137018ff290
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper-a64.c
M target/arm/helper.c
Log Message:
-----------
target/arm: use arm_is_el2_enabled() where applicable
Do not assume that EL2 is available in and only in non-secure context.
That equivalence is broken by ARMv8.4-SEL2.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-3-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e04a5752cb03e066d7b1e583e340c7982fcd5e4e
https://github.com/qemu/qemu/commit/e04a5752cb03e066d7b1e583e340c7982fcd5e4e
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: use arm_hcr_el2_eff() where applicable
This will simplify accessing HCR conditionally in secure state.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-4-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 59dd089cf9e4a9cddee596c8a1378620df51b9bb
https://github.com/qemu/qemu/commit/59dd089cf9e4a9cddee596c8a1378620df51b9bb
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: factor MDCR_EL2 common handling
This adds a common helper to compute the effective value of MDCR_EL2.
That is the actual value if EL2 is enabled in the current security
context, or 0 elsewise.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-5-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5ca192dfc551c8a40871c4e30a8b8ceb879adc31
https://github.com/qemu/qemu/commit/5ca192dfc551c8a40871c4e30a8b8ceb879adc31
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Define isar_feature function to test for presence of SEL2
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-6-remi.denis.courmont@huawei.com
[PMM: tweaked commit message to match reduced scope of patch
following rebase]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6c85f906261226e87211506bd9f787fd48a09f17
https://github.com/qemu/qemu/commit/6c85f906261226e87211506bd9f787fd48a09f17
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/helper.c
M target/arm/op_helper.c
Log Message:
-----------
target/arm: add 64-bit S-EL2 to EL exception table
With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in
secure mode, though it can only be AArch64.
This patch adds the target EL for exceptions from 64-bit S-EL2.
It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure
mode. Those values were never used in practice as the effective value of
HCR was always 0 in secure mode.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-7-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b6ad6062f1e55bd5b9407ce89e55e3a08b83827c
https://github.com/qemu/qemu/commit/b6ad6062f1e55bd5b9407ce89e55e3a08b83827c
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/cpu-param.h
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: add MMU stage 1 for Secure EL2
This adds the MMU indices for EL2 stage 1 in secure state.
To keep code contained, which is largelly identical between secure and
non-secure modes, the MMU indices are reassigned. The new assignments
provide a systematic pattern with a non-secure bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-8-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e9152ee91cc39ed8a53d03607e6e980a7e9444e6
https://github.com/qemu/qemu/commit/e9152ee91cc39ed8a53d03607e6e980a7e9444e6
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: add ARMv8.4-SEL2 system registers
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-9-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c4f060e89effd70ebdb23d3315495d33af377a09
https://github.com/qemu/qemu/commit/c4f060e89effd70ebdb23d3315495d33af377a09
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: handle VMID change in secure state
The VTTBR write callback so far assumes that the underlying VM lies in
non-secure state. This handles the secure state scenario.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-10-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3d4bd397433b12b148d150c8bc5655a696389bd1
https://github.com/qemu/qemu/commit/3d4bd397433b12b148d150c8bc5655a696389bd1
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: do S1_ptw_translate() before address space lookup
In the secure stage 2 translation regime, the VSTCR.SW and VTCR.NSW
bits can invert the secure flag for pagetable walks. This patchset
allows S1_ptw_translate() to change the non-secure bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-11-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 588c6dd113b27b8db393c7264297b9d33261692e
https://github.com/qemu/qemu/commit/588c6dd113b27b8db393c7264297b9d33261692e
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: translate NS bit in page-walks
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-12-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7879460a6149ed5e80c29cac85449191d9c5754a
https://github.com/qemu/qemu/commit/7879460a6149ed5e80c29cac85449191d9c5754a
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: generalize 2-stage page-walk condition
The stage_1_mmu_idx() already effectively keeps track of which
translation regimes have two stages. Don't hard-code another test.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-13-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b1a10c868f9b2b09e64009b43450e9a86697d9f3
https://github.com/qemu/qemu/commit/b1a10c868f9b2b09e64009b43450e9a86697d9f3
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: secure stage 2 translation regime
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-14-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9861248f637ecf11113b04b0b5c7b13c9aa06f09
https://github.com/qemu/qemu/commit/9861248f637ecf11113b04b0b5c7b13c9aa06f09
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/tlb_helper.c
Log Message:
-----------
target/arm: set HPFAR_EL2.NS on secure stage 2 faults
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-15-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6b340aeb48e4f7f983e1c38790de65ae93079840
https://github.com/qemu/qemu/commit/6b340aeb48e4f7f983e1c38790de65ae93079840
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: revector to run-time pick target EL
On ARMv8-A, accesses by 32-bit secure EL1 to monitor registers trap to
the upper (64-bit) EL. With Secure EL2 support, we can no longer assume
that that is always EL3, so make room for the value to be computed at
run-time.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-16-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 926c1b97895879b78ca14bca2831c08740ed1c38
https://github.com/qemu/qemu/commit/926c1b97895879b78ca14bca2831c08740ed1c38
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement SCR_EL2.EEL2
This adds handling for the SCR_EL3.EEL2 bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Message-id: 20210112104511.36576-17-remi.denis.courmont@huawei.com
[PMM: Applied fixes for review issues noted by RTH:
- check for FEATURE_AARCH64 before checking sel2 isar feature
- correct the commit message subject line]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 24179fea7e34c4952d4878ae1b26108ba65e5933
https://github.com/qemu/qemu/commit/24179fea7e34c4952d4878ae1b26108ba65e5933
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: enable Secure EL2 in max CPU
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-18-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bc944d3a8b305029196a5e1406702a92fa0b94cf
https://github.com/qemu/qemu/commit/bc944d3a8b305029196a5e1406702a92fa0b94cf
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: refactor vae1_tlbmask()
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-19-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b64ee454a4a086ed459bcda4c0bbb54e197841e4
https://github.com/qemu/qemu/commit/b64ee454a4a086ed459bcda4c0bbb54e197841e4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/internals.h
Log Message:
-----------
target/arm: Introduce PREDDESC field definitions
SVE predicate operations cannot use the "usual" simd_desc
encoding, because the lengths are not a multiple of 8.
But we were abusing the SIMD_* fields to store values anyway.
This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a214.
Introduce a new set of field definitions for exclusive use
of predicates, so that it is obvious what kind of predicate
we are manipulating. To be used in future patches.
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210113062650.593824-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 86300b5d044064046395ae8ed605cc19e63f2a7c
https://github.com/qemu/qemu/commit/86300b5d044064046395ae8ed605cc19e63f2a7c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Update PFIRST, PNEXT for pred_desc
These two were odd, in that do_pfirst_pnext passed the
count of 64-bit words rather than bytes. Change to pass
the standard pred_full_reg_size to avoid confusion.
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210113062650.593824-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f9b0fcceccfc05cde62ff7577fbf2bc13b842414
https://github.com/qemu/qemu/commit/f9b0fcceccfc05cde62ff7577fbf2bc13b842414
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Update ZIP, UZP, TRN for pred_desc
Update all users of do_perm_pred3 for the new
predicate descriptor field definitions.
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210113062650.593824-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 70acaafef2e053a312d54c09b6721c730690e72c
https://github.com/qemu/qemu/commit/70acaafef2e053a312d54c09b6721c730690e72c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Update REV, PUNPK for pred_desc
Update all users of do_perm_pred2 for the new
predicate descriptor field definitions.
Cc: qemu-stable@nongnu.org
Buglink: https://bugs.launchpad.net/bugs/1908551
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210113062650.593824-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 73624e04a5381c3046109e4d4ec796e66b9dbd95
https://github.com/qemu/qemu/commit/73624e04a5381c3046109e4d4ec796e66b9dbd95
Author: Gan Qixin <ganqixin@huawei.com>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M tests/qtest/npcm7xx_adc-test.c
Log Message:
-----------
npcm7xx_adc-test: Fix memleak in adc_qom_set
The adc_qom_set function didn't free "response", which caused an indirect
memory leak. So use qobject_unref() to fix it.
ASAN shows memory leak stack:
Indirect leak of 593280 byte(s) in 144 object(s) allocated from:
#0 0x7f9a5e7e8d4e in __interceptor_calloc (/lib64/libasan.so.5+0x112d4e)
#1 0x7f9a5e607a50 in g_malloc0 (/lib64/libglib-2.0.so.0+0x55a50)
#2 0x55b1bebf636b in qdict_new ../qobject/qdict.c:30
#3 0x55b1bec09699 in parse_object ../qobject/json-parser.c:318
#4 0x55b1bec0b2df in parse_value ../qobject/json-parser.c:546
#5 0x55b1bec0b6a9 in json_parser_parse ../qobject/json-parser.c:580
#6 0x55b1bec060d1 in json_message_process_token
../qobject/json-streamer.c:92
#7 0x55b1bec16a12 in json_lexer_feed_char ../qobject/json-lexer.c:313
#8 0x55b1bec16fbd in json_lexer_feed ../qobject/json-lexer.c:350
#9 0x55b1bec06453 in json_message_parser_feed ../qobject/json-streamer.c:121
#10 0x55b1bebc2d51 in qmp_fd_receive ../tests/qtest/libqtest.c:614
#11 0x55b1bebc2f5e in qtest_qmp_receive_dict ../tests/qtest/libqtest.c:636
#12 0x55b1bebc2e6c in qtest_qmp_receive ../tests/qtest/libqtest.c:624
#13 0x55b1bebc3340 in qtest_vqmp ../tests/qtest/libqtest.c:715
#14 0x55b1bebc3942 in qtest_qmp ../tests/qtest/libqtest.c:756
#15 0x55b1bebbd64a in adc_qom_set ../tests/qtest/npcm7xx_adc-test.c:127
#16 0x55b1bebbd793 in adc_write_input ../tests/qtest/npcm7xx_adc-test.c:140
#17 0x55b1bebbdf92 in test_convert_external
../tests/qtest/npcm7xx_adc-test.c:246
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210118065627.79903-1-ganqixin@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0ae4f11ee57350dac0e705ba79516310400ff43c
https://github.com/qemu/qemu/commit/0ae4f11ee57350dac0e705ba79516310400ff43c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M target/arm/m_helper.c
Log Message:
-----------
target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
When building with GCC 10.2 configured with --extra-cflags=-Os, we get:
target/arm/m_helper.c: In function ‘arm_v7m_cpu_do_interrupt’:
target/arm/m_helper.c:1811:16: error: ‘restore_s16_s31’ may be used
uninitialized in this function [-Werror=maybe-uninitialized]
1811 | if (restore_s16_s31) {
| ^
target/arm/m_helper.c:1350:10: note: ‘restore_s16_s31’ was declared here
1350 | bool restore_s16_s31;
| ^~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Initialize the 'restore_s16_s31' variable to silence the warning.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210119062739.589049-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b93f4fbdc48283a39089469c44a5529d79dc40a8
https://github.com/qemu/qemu/commit/b93f4fbdc48283a39089469c44a5529d79dc40a8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M .gitlab-ci.yml
M docs/conf.py
R docs/devel/conf.py
R docs/index.html.in
R docs/interop/conf.py
M docs/meson.build
R docs/specs/conf.py
R docs/system/conf.py
R docs/tools/conf.py
R docs/user/conf.py
Log Message:
-----------
docs: Build and install all the docs in a single manual
When we first converted our documentation to Sphinx, we split it into
multiple manuals (system, interop, tools, etc), which are all built
separately. The primary driver for this was wanting to be able to
avoid shipping the 'devel' manual to end-users. However, this is
working against the grain of the way Sphinx wants to be used and
causes some annoyances:
* Cross-references between documents become much harder or
possibly impossible
* There is no single index to the whole documentation
* Within one manual there's no links or table-of-contents info
that lets you easily navigate to the others
* The devel manual doesn't get published on the QEMU website
(it would be nice to able to refer to it there)
Merely hiding our developer documentation from end users seems like
it's not enough benefit for these costs. Combine all the
documentation into a single manual (the same way that the readthedocs
site builds it) and install the whole thing. The previous manual
divisions remain as the new top level sections in the manual.
* The per-manual conf.py files are no longer needed
* The man_pages[] specifications previously in each per-manual
conf.py move to the top level conf.py
* docs/meson.build logic is simplified as we now only need to run
Sphinx once for the HTML and then once for the manpages5B
* The old index.html.in that produced the top-level page with
links to each manual is no longer needed
Unfortunately this means that we now have to build the HTML
documentation into docs/manual in the build tree rather than directly
into docs/; otherwise it is too awkward to ensure we install only the
built manual and not also the dependency info, stamp file, etc. The
manual still ends up in the same place in the final installed
directory, but anybody who was consulting documentation from within
the build tree will have to adjust where they're looking.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20210115154449.4801-1-peter.maydell@linaro.org
Commit: 48202c712412c803ddb56365c7bca322aa4e7506
https://github.com/qemu/qemu/commit/48202c712412c803ddb56365c7bca322aa4e7506
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-01-19 (Tue, 19 Jan 2021)
Changed paths:
M .gitlab-ci.yml
M docs/conf.py
R docs/devel/conf.py
R docs/index.html.in
R docs/interop/conf.py
M docs/meson.build
R docs/specs/conf.py
M docs/system/arm/cpu-features.rst
R docs/system/conf.py
R docs/tools/conf.py
R docs/user/conf.py
M include/qemu/xxhash.h
M target/arm/cpu-param.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper-a64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/m_helper.c
M target/arm/monitor.c
M target/arm/op_helper.c
M target/arm/pauth_helper.c
M target/arm/sve_helper.c
M target/arm/tlb_helper.c
M target/arm/translate-a64.c
M target/arm/translate-sve.c
M target/arm/translate.c
M tests/qtest/arm-cpu-features.c
M tests/qtest/npcm7xx_adc-test.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20210119-1' into staging
target-arm queue:
* Implement IMPDEF pauth algorithm
* Support ARMv8.4-SEL2
* Fix bug where we were truncating predicate vector lengths in SVE insns
* npcm7xx_adc-test: Fix memleak in adc_qom_set
* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
* docs: Build and install all the docs in a single manual
# gpg: Signature made Tue 19 Jan 2021 15:46:34 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210119-1: (29 commits)
docs: Build and install all the docs in a single manual
target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
npcm7xx_adc-test: Fix memleak in adc_qom_set
target/arm: Update REV, PUNPK for pred_desc
target/arm: Update ZIP, UZP, TRN for pred_desc
target/arm: Update PFIRST, PNEXT for pred_desc
target/arm: Introduce PREDDESC field definitions
target/arm: refactor vae1_tlbmask()
target/arm: enable Secure EL2 in max CPU
target/arm: Implement SCR_EL2.EEL2
target/arm: revector to run-time pick target EL
target/arm: set HPFAR_EL2.NS on secure stage 2 faults
target/arm: secure stage 2 translation regime
target/arm: generalize 2-stage page-walk condition
target/arm: translate NS bit in page-walks
target/arm: do S1_ptw_translate() before address space lookup
target/arm: handle VMID change in secure state
target/arm: add ARMv8.4-SEL2 system registers
target/arm: add MMU stage 1 for Secure EL2
target/arm: add 64-bit S-EL2 to EL exception table
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/f1fcb6851aba...48202c712412