[Qemu-commits] [qemu/qemu] 709616: util/cutils: Introduce freq_to

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[Qemu-commits] [qemu/qemu] 709616: util/cutils: Introduce freq_to_str()

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 709616: util/cutils: Introduce freq_to_str() to display He...
Date:	Mon, 19 Oct 2020 03:45:43 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 709616c713f9471a993ad7d16bce23e8b88ce958
      
https://github.com/qemu/qemu/commit/709616c713f9471a993ad7d16bce23e8b88ce958
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-16 (Fri, 16 Oct 2020)

  Changed paths:
    M include/qemu/cutils.h
    M util/cutils.c

  Log Message:
  -----------
  util/cutils: Introduce freq_to_str() to display Hertz units

Introduce freq_to_str() to convert frequency values in human
friendly units using the SI units for Hertz.

Suggested-by: Luc Michel <luc@lmichel.fr>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-Id: <20201012095804.3335117-2-f4bug@amsat.org>


  Commit: 01d858629eae532f50f3dac6df9e6ab912626e00
      
https://github.com/qemu/qemu/commit/01d858629eae532f50f3dac6df9e6ab912626e00
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-16 (Fri, 16 Oct 2020)

  Changed paths:
    M hw/core/qdev-clock.c

  Log Message:
  -----------
  hw/qdev-clock: Display error hint when clock is missing from device

Instead of directly aborting, display a hint to help the developer
figure out the problem (likely trying to connect a clock to a device
pre-dating the Clock API, thus not expecting clocks).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <20201012095804.3335117-4-f4bug@amsat.org>


  Commit: 5ebc664800b66f886f58cd4d5bcc7785644c9980
      
https://github.com/qemu/qemu/commit/5ebc664800b66f886f58cd4d5bcc7785644c9980
  Author: Luc Michel <luc@lmichel.fr>
  Date:   2020-10-16 (Fri, 16 Oct 2020)

  Changed paths:
    M hw/core/clock.c
    M include/hw/clock.h

  Log Message:
  -----------
  hw/core/clock: Add the clock_new helper function

This function creates a clock and parents it to another object with a
given name. It calls clock_setup_canonical_path before returning the
new clock.

This function is useful to create clocks in devices when one doesn't
want to expose it at the qdev level (as an input or an output).

Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201010135759.437903-4-luc@lmichel.fr>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 8cdf88690dc79511cfa1b2557434c09e3685f090
      
https://github.com/qemu/qemu/commit/8cdf88690dc79511cfa1b2557434c09e3685f090
  Author: zhaolichang <zhaolichang@huawei.com>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/internal.h
    M target/mips/translate.c
    M target/mips/translate_init.c.inc

  Log Message:
  -----------
  target/mips: Fix some comment spelling errors

There are many spelling errors in the comments in target/mips/.
Use spellcheck to check the spelling errors.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
Reviewed-by: David Edmondson <david.edmondson@oracle.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201009064449.2336-7-zhaolichang@huawei.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 8a6c9e0fdd10dce2240b2058fdedc5557e36adbd
      
https://github.com/qemu/qemu/commit/8a6c9e0fdd10dce2240b2058fdedc5557e36adbd
  Author: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/fpu_helper.c

  Log Message:
  -----------
  target/mips: Demacro helpers for <ABS|CHS>.<D|S|PS>

Remove function definitions via macros to achieve better code clarity.

Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1602103041-32017-2-git-send-email-aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: be0cb99426badb2fa0b02404144b2b80ac82f4c9
      
https://github.com/qemu/qemu/commit/be0cb99426badb2fa0b02404144b2b80ac82f4c9
  Author: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/fpu_helper.c

  Log Message:
  -----------
  target/mips: Demacro helpers for M<ADD|SUB>F.<D|S>

Remove function definitions via macros to achieve better code clarity.

Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1602103041-32017-3-git-send-email-aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 32eb97b5eb24c1fc1a1c366f25e1ffe31f0e096a
      
https://github.com/qemu/qemu/commit/32eb97b5eb24c1fc1a1c366f25e1ffe31f0e096a
  Author: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/fpu_helper.c

  Log Message:
  -----------
  target/mips: Demacro helpers for <MAX|MAXA|MIN|MINA>.<D|S>

Remove function definitions via macros to achieve better code clarity.

Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1602103041-32017-4-git-send-email-aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: e10a0ca17dfeac25afb58f163b99d784b88d4e23
      
https://github.com/qemu/qemu/commit/e10a0ca17dfeac25afb58f163b99d784b88d4e23
  Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add loongson-ext lswc2 group of instructions (Part 1)

LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.

This patch add implementation of these instructions:

  gslq: load 16 bytes to GPR
  gssq: store 16 bytes from GPR
  gslqc1: load 16 bytes to FPR
  gssqc1: store 16 bytes from FPR

Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <1602831120-3377-3-git-send-email-chenhc@lemote.com>
[PMD: Restrict t1 variable to TARGET_MIPS64, remove unused t2/fp0]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: fd723105c15e09b8a9eaad29fa59347e63cfdb20
      
https://github.com/qemu/qemu/commit/fd723105c15e09b8a9eaad29fa59347e63cfdb20
  Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add loongson-ext lswc2 group of instructions (Part 2)

LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.

This patch add implementation of these instructions:

  gslwlc1: similar to lwl but RT is FPR instead of GPR
  gslwrc1: similar to lwr but RT is FPR instead of GPR
  gsldlc1: similar to ldl but RT is FPR instead of GPR
  gsldrc1: similar to ldr but RT is FPR instead of GPR
  gsswlc1: similar to swl but RT is FPR instead of GPR
  gsswrc1: similar to swr but RT is FPR instead of GPR
  gssdlc1: similar to sdl but RT is FPR instead of GPR
  gssdrc1: similar to sdr but RT is FPR instead of GPR

Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <1602831120-3377-4-git-send-email-chenhc@lemote.com>
[PMD: Reuse t1 on MIPS32, reintroduce t2/fp0]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 90e22a57af975dea08b3015dfac072709f131616
      
https://github.com/qemu/qemu/commit/90e22a57af975dea08b3015dfac072709f131616
  Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add loongson-ext lsdc2 group of instructions

LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
group of instructions by loongson-ext ASE.

This patch add implementation of these instructions:

  gslbx: load 1 bytes to GPR
  gslhx: load 2 bytes to GPR
  gslwx: load 4 bytes to GPR
  gsldx: load 8 bytes to GPR
  gslwxc1: load 4 bytes to FPR
  gsldxc1: load 8 bytes to FPR
  gssbx: store 1 bytes from GPR
  gsshx: store 2 bytes from GPR
  gsswx: store 4 bytes from GPR
  gssdx: store 8 bytes from GPR
  gsswxc1: store 4 bytes from FPR
  gssdxc1: store 8 bytes from FPR

Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1602831120-3377-5-git-send-email-chenhc@lemote.com>


  Commit: 4a367cfb00d3779f0113f871e4b7cb550d068098
      
https://github.com/qemu/qemu/commit/4a367cfb00d3779f0113f871e4b7cb550d068098
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips/op_helper: Convert multiple if() to switch case

The cache operation is encoded in bits [20:18] of the instruction.
The 'op' argument of helper_cache() contains the bits [20:16].
Extract the 3 bits and parse them using a switch case. This allow
us to handle multiple cache types (the cache type is encoded in
bits [17:16]).

Previously the if() block was only checking the D-Cache (Primary
Data or Unified Primary). Now we also handle the I-Cache (Primary
Instruction), S-Cache (Secondary) and T-Cache (Terciary).

Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20200813181527.22551-2-f4bug@amsat.org>


  Commit: 45964263e42b9728dd206936c157bfd1bdb6918a
      
https://github.com/qemu/qemu/commit/45964263e42b9728dd206936c157bfd1bdb6918a
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op

QEMU does not model caches, so there is not much to do with the
Invalidate/Writeback opcodes. Make it explicit adding a comment.

Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20200813181527.22551-3-f4bug@amsat.org>


  Commit: 88a844545e0fb1fa95a55888fb31024fcfc9720b
      
https://github.com/qemu/qemu/commit/88a844545e0fb1fa95a55888fb31024fcfc9720b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips/op_helper: Log unimplemented cache opcode

In case the guest uses a cache opcode we are not expecting,
log it to give us a chance to notice it, in case we should
actually do something.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20200813181527.22551-4-f4bug@amsat.org>


  Commit: 2dc29222a6f7c87300c1a7e1982e11422d34595e
      
https://github.com/qemu/qemu/commit/2dc29222a6f7c87300c1a7e1982e11422d34595e
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/cp0_helper.c
    M target/mips/cp0_timer.c
    M target/mips/internal.h

  Log Message:
  -----------
  target/mips: Move cpu_mips_get_random() with CP0 helpers

The get_random() helper uses the CP0_Wired register, which is
unrelated to the CP0_Count register used as timer.
Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file")
incorrectly moved this get_random() helper with timer specific
code. Move it back to generic CP0 helpers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-Id: <20201012095804.3335117-6-f4bug@amsat.org>


  Commit: 62f8f2603da7fbcc481489d2903558001a896cad
      
https://github.com/qemu/qemu/commit/62f8f2603da7fbcc481489d2903558001a896cad
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/cp0_timer.c

  Log Message:
  -----------
  target/mips/cp0_timer: Explicit unit in variable name

Name variables holding nanoseconds with the '_ns' suffix.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20201012095804.3335117-7-f4bug@amsat.org>


  Commit: 8dadffc01700f79fd66db972fff3a93a594715ee
      
https://github.com/qemu/qemu/commit/8dadffc01700f79fd66db972fff3a93a594715ee
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/cp0_timer.c

  Log Message:
  -----------
  target/mips/cp0_timer: Document TIMER_PERIOD origin

TIMER_PERIOD value of '10 ns' can be explained looking at
commit 6af0bf9c7c3doc, where the CPU frequency is 200 MHz
and CP0 default count rate is half the frequency of the
CPU. Document that.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-8-f4bug@amsat.org>


  Commit: d225b5122029c3d6293aab6e2d0a05597fc92ba4
      
https://github.com/qemu/qemu/commit/d225b5122029c3d6293aab6e2d0a05597fc92ba4
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/cp0_timer.c
    M target/mips/cpu.c
    M target/mips/cpu.h

  Log Message:
  -----------
  target/mips: Move cp0_count_ns to CPUMIPSState

Currently the CP0 timer period is fixed at 10 ns, corresponding
to a fixed CPU frequency of 200 MHz (using half the speed of the
CPU).

In few commits we will be able to use a different CPU frequency.
In preparation, move the cp0_count_ns variable to CPUMIPSState
so we can modify it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-9-f4bug@amsat.org>


  Commit: 68b981aa76079216f5765a6aecaf8728f27d3696
      
https://github.com/qemu/qemu/commit/68b981aa76079216f5765a6aecaf8728f27d3696
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/cpu.c

  Log Message:
  -----------
  target/mips/cpu: Calculate the CP0 timer period using the CPU frequency

The CP0 timer period is a function of the CPU frequency.
Start using the default values, which will be replaced by
properties in the next commits.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-10-f4bug@amsat.org>


  Commit: d0bec217ee0f6c948ba4579ca0f43a1a3f346cb4
      
https://github.com/qemu/qemu/commit/d0bec217ee0f6c948ba4579ca0f43a1a3f346cb4
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/cpu.c
    M target/mips/cpu.h

  Log Message:
  -----------
  target/mips/cpu: Make cp0_count_rate a property

Since not all CPU implementations use a cores use a CP0 timer
at half the frequency of the CPU, make this variable a property.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-11-f4bug@amsat.org>


  Commit: a0713e85bfaec4d787b978640096322716938a56
      
https://github.com/qemu/qemu/commit/a0713e85bfaec4d787b978640096322716938a56
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/cpu.c
    M target/mips/cpu.h

  Log Message:
  -----------
  target/mips/cpu: Allow the CPU to use dynamic frequencies

Use the Clock API and let the CPU object have an input clock.

If no clock is connected, keep using the default frequency of
200 MHz used since the introduction of the 'r4k' machine in
commit 6af0bf9c7c3.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-12-f4bug@amsat.org>


  Commit: 7aaab96a9b1c37f473f73363ff815eb059a2f823
      
https://github.com/qemu/qemu/commit/7aaab96a9b1c37f473f73363ff815eb059a2f823
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/cpu.c
    M target/mips/cpu.h

  Log Message:
  -----------
  target/mips/cpu: Introduce mips_cpu_create_with_clock() helper

Introduce an helper to create a MIPS CPU and connect it to
a reference clock. This helper is not MIPS specific, but so
far only MIPS CPUs need it.

Suggested-by: Huacai Chen <zltjiangshi@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-13-f4bug@amsat.org>


  Commit: dccf092d67e05c76fe47ed92cab0aa59e77c6e08
      
https://github.com/qemu/qemu/commit/dccf092d67e05c76fe47ed92cab0aa59e77c6e08
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/r4k.c

  Log Message:
  -----------
  hw/mips/r4k: Explicit CPU frequency is 200 MHz

Since its introduction in commit 6af0bf9c7c3,
the 'r4k' machine runs at 200 MHz.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-14-f4bug@amsat.org>


  Commit: 3ca7639ff0077ef1869c88523360c017defecaad
      
https://github.com/qemu/qemu/commit/3ca7639ff0077ef1869c88523360c017defecaad
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/fuloong2e.c

  Log Message:
  -----------
  hw/mips/fuloong2e: Set CPU frequency to 533 MHz

The CPU frequency is normally provided by the firmware in the
"cpuclock" environment variable. The 2E board can handles up
to 660MHz, but be conservative and take the same value used
by the Linux kernel: 533 MHz.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-15-f4bug@amsat.org>


  Commit: 8543a806912da7cdbc45303226762372f92f689b
      
https://github.com/qemu/qemu/commit/8543a806912da7cdbc45303226762372f92f689b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/mipssim.c

  Log Message:
  -----------
  hw/mips/mipssim: Correct CPU frequency

The MIPSsim machine CPU frequency is too fast running at 200 MHz,
while it should be 12 MHz for the 24K and 6 MHz for the 5K core.

Ref: Linux commit c78cbf49c4ed
("Support for MIPSsim, the cycle accurate MIPS simulator.")

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-16-f4bug@amsat.org>


  Commit: 79b99fe3f09979b6ba0a8d9f4603dc43e7e066c4
      
https://github.com/qemu/qemu/commit/79b99fe3f09979b6ba0a8d9f4603dc43e7e066c4
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/jazz.c

  Log Message:
  -----------
  hw/mips/jazz: Correct CPU frequencies

The Magnum 4000PC CPU runs at 100 MHz, and the Acer PICA-61
CPU at ~134 MHz.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-17-f4bug@amsat.org>


  Commit: e8373c56531cec8eb48743f261e8b216bcda589a
      
https://github.com/qemu/qemu/commit/e8373c56531cec8eb48743f261e8b216bcda589a
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/cps.c
    M include/hw/mips/cps.h

  Log Message:
  -----------
  hw/mips/cps: Expose input clock and connect it to CPU cores

Expose a qdev input clock named 'clk-in', and connect it to each
core to forward-propagate the clock.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-18-f4bug@amsat.org>


  Commit: 6b290b41cb533b93548248846e0e320af0a419ed
      
https://github.com/qemu/qemu/commit/6b290b41cb533b93548248846e0e320af0a419ed
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/boston.c

  Log Message:
  -----------
  hw/mips/boston: Set CPU frequency to 1 GHz

The I6400 can run at 1 GHz or more. Create a 'cpuclk'
output clock and connect it to the CPU input clock.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-19-f4bug@amsat.org>


  Commit: eea1f5bac6f7ea71ef357bb8166512ef759a7b32
      
https://github.com/qemu/qemu/commit/eea1f5bac6f7ea71ef357bb8166512ef759a7b32
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/malta.c

  Log Message:
  -----------
  hw/mips/malta: Set CPU frequency to 320 MHz

The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create
a 'cpuclk' output clock and connect it to the CPU input clock.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-20-f4bug@amsat.org>


  Commit: ba25670c1d3e122bfa5a43cd785f5eb4988861d9
      
https://github.com/qemu/qemu/commit/ba25670c1d3e122bfa5a43cd785f5eb4988861d9
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/cps.c

  Log Message:
  -----------
  hw/mips/cps: Do not allow use without input clock

Now than all QOM users provides the input clock, do not allow
using a CPS without input clock connected.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-21-f4bug@amsat.org>


  Commit: 8a6359f937632d4b47bfaf0640c5acbf73736521
      
https://github.com/qemu/qemu/commit/8a6359f937632d4b47bfaf0640c5acbf73736521
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/cpu.c

  Log Message:
  -----------
  target/mips/cpu: Display warning when CPU is used without input clock

All our QOM users provides an input clock. In order to avoid
avoid future machines added without clock, display a warning.

User-mode emulation use the CP0 timer with the RDHWR instruction
(see commit cdfcad788394) so keep using the fixed 200 MHz clock
without diplaying any warning. Only display it in system-mode
emulation.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-22-f4bug@amsat.org>


  Commit: 9a2133f45c287e99ef23896a7a33b3d2dbfe97fd
      
https://github.com/qemu/qemu/commit/9a2133f45c287e99ef23896a7a33b3d2dbfe97fd
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/malta.c

  Log Message:
  -----------
  hw/mips/malta: Fix FPGA I/O region size

The FPGA present on the CoreCard has an I/O region 1MiB wide.

Refs:
- Atlas User’s Manual (Document Number: MD00005)
- Malta User’s Manual (Document Number: MD00048)

Fixes: ea85df72b60 ("mips_malta: convert to memory API")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200905213049.761949-1-f4bug@amsat.org>


  Commit: c5cdf7561311a2dd37eb7af636247440182e6e0b
      
https://github.com/qemu/qemu/commit/c5cdf7561311a2dd37eb7af636247440182e6e0b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/malta.c

  Log Message:
  -----------
  hw/mips/malta: Move gt64120 related code together

The 'empty_slot' region created is related to the gt64120.
Move its creation close to the gt64120 instance creation.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201012160503.3472140-2-f4bug@amsat.org>


  Commit: 8df525a558e85aee7a2c757dd7654173ef369544
      
https://github.com/qemu/qemu/commit/8df525a558e85aee7a2c757dd7654173ef369544
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/malta.c

  Log Message:
  -----------
  hw/mips/malta: Use clearer qdev style

In order to be consistent with the other code base uses,
rewrite slightly how the MIPS_MALTA object is created.
No logical change.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201012160503.3472140-3-f4bug@amsat.org>


  Commit: 9d585eaa87bf1c5f66e12d6c4a8a38c80f69c5da
      
https://github.com/qemu/qemu/commit/9d585eaa87bf1c5f66e12d6c4a8a38c80f69c5da
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/mipssim.c
    M hw/mips/r4k.c

  Log Message:
  -----------
  hw/mips: Simplify loading 64-bit ELF kernels

Since 82790064116 ("Cast ELF datatypes properly to host 64bit types")
we don't need to sign-extend the entry_point address. Remove this
unnecessary code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200927163943.614604-2-f4bug@amsat.org>


  Commit: acab36ca25101930b263dd9e8afd9b244354d338
      
https://github.com/qemu/qemu/commit/acab36ca25101930b263dd9e8afd9b244354d338
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/fuloong2e.c
    M hw/mips/malta.c
    M hw/mips/mipssim.c
    M hw/mips/r4k.c
    M include/hw/mips/mips.h

  Log Message:
  -----------
  hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)

Instead of using a INITRD_PAGE_MASK definition, use the
simpler INITRD_PAGE_SIZE one which allows us to simplify
the code by using directly the self-explicit ROUND_UP()
macro.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200927163943.614604-3-f4bug@amsat.org>


  Commit: 27cf0896bfd84a9ccb2cfe315952338f00aa086e
      
https://github.com/qemu/qemu/commit/27cf0896bfd84a9ccb2cfe315952338f00aa086e
  Author: Eduardo Habkost <ehabkost@redhat.com>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/boston.c

  Log Message:
  -----------
  hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON

This will make the type name constant consistent with the name of
the type checking macro.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200902224311.1321159-19-ehabkost@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: a4374f86dc648b6cf10a7c8c40bde33722e5b25d
      
https://github.com/qemu/qemu/commit/a4374f86dc648b6cf10a7c8c40bde33722e5b25d
  Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M hw/mips/fuloong2e.c
    M hw/mips/jazz.c
    M hw/mips/malta.c
    M hw/mips/mipssim.c

  Log Message:
  -----------
  hw/mips: Remove exit(1) in case of missing ROM

This patch updates MIPS-based machines to allow starting them without ROM.
In this case CPU starts to execute instructions from the empty memory,
but QEMU allows introspecting the machine configuration.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <159531210571.24117.231100997794891819.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 1d2ff14b72ed11d577cbe42a3fef9fcce522418a
      
https://github.com/qemu/qemu/commit/1d2ff14b72ed11d577cbe42a3fef9fcce522418a
  Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M tests/acceptance/replay_kernel.py

  Log Message:
  -----------
  tests/acceptance: Add MIPS record/replay tests

This patch adds MIPS-targeted acceptance tests for
record/replay functions.

Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <160276110297.2705.10918105269658307206.stgit@pasha-ThinkPad-X280>
[PMD: Moved 'override timeout' comment from instance to class,
      moved nanomips tests to ReplayKernelSlow class,
      tagged ReplayKernelSlow class with AVOCADO_TIMEOUT_EXPECTED]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: b5330cf19ad29a71c3981d315a14f17db539ec80
      
https://github.com/qemu/qemu/commit/b5330cf19ad29a71c3981d315a14f17db539ec80
  Author: Huacai Chen <zltjiangshi@gmail.com>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M docs/system/cpu-models-mips.rst.inc

  Log Message:
  -----------
  docs/system: Update MIPS CPU documentation

Add Loongson-3A CPU models description.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <1602059975-10115-10-git-send-email-chenhc@lemote.com>
[PMD: Split patch in 2: CPU / machine]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: ca263c0fb9f33cc746e6e3d968b7db80072ecf86
      
https://github.com/qemu/qemu/commit/ca263c0fb9f33cc746e6e3d968b7db80072ecf86
  Author: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Remove myself

I have been working on project other than QEMU for some time, and would
like to devote myself to that project. It is impossible for me to find
enough time to perform maintainer's duties with needed meticulousness
and patience.

I wish prosperous future to QEMU and all colleagues in QEMU community.

Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1602103041-32017-6-git-send-email-aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: cf960317cb644c772610c1a275a88635af4a40d9
      
https://github.com/qemu/qemu/commit/cf960317cb644c772610c1a275a88635af4a40d9
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Put myself forward for MIPS target

To avoid the MIPS target being orphan, volunteer to keep an eye
on it and put together pull requests.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20201013101659.3557154-2-f4bug@amsat.org>


  Commit: 4ba98e96e0d1cf8c6188a3169fbb2e1f08838a63
      
https://github.com/qemu/qemu/commit/4ba98e96e0d1cf8c6188a3169fbb2e1f08838a63
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton mail

Paul's Wavecomp email has been bouncing for months. He told us
he "no longer has access to modern MIPS CPUs or Boston hardware,
and wouldn't currently have time to spend on them if he did." [1]
but "perhaps that might change in the future." [2].
Be fair and downgrade the status of the Boston board to "Odd Fixes"
(has a maintainer but they don't have time to do much other).
Similarly to commit 2b107c2c1c (".mailmap: Update Paul Burton email
address"), update his email address here too.

[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg718739.html
[2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg728605.html

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20201013101659.3557154-4-f4bug@amsat.org>


  Commit: 5ca2b252692761e9c7bea60634d3ecca96be0599
      
https://github.com/qemu/qemu/commit/5ca2b252692761e9c7bea60634d3ecca96be0599
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Remove duplicated Malta test entries

The Malta tests are already covered in the Malta section.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20201013101659.3557154-3-f4bug@amsat.org>


  Commit: 68fa519a6cb455005317bd61f95214b58b2f1e69
      
https://github.com/qemu/qemu/commit/68fa519a6cb455005317bd61f95214b58b2f1e69
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M target/mips/translate_init.c.inc

  Log Message:
  -----------
  target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)

Per "MIPS32 34K Processor Core Family Software User's Manual,
Revision 01.13" page 8 in "Joint TLB (JTLB)" section:

  "The JTLB is a fully associative TLB cache containing 16, 32,
   or 64-dual-entries mapping up to 128 virtual pages to their
   corresponding physical addresses."

There is no particular reason to restrict the 34Kf core model to
16 TLB entries, so raise its config to 64.

This is helpful for other projects, in particular the Yocto Project:

  Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit
  MIPS CI loop. It was observed that in this case CI test execution
  time was almost twice longer than 64bit MIPS variant that runs
  under MIPS64R2-generic model. It was investigated and concluded
  that the difference in number of TLBs 16 in 34Kf case vs 64 in
  MIPS64R2-generic is responsible for most of CI real time execution
  difference. Because with 16 TLBs linux user-land trashes TLB more
  and it needs to execute more instructions in TLB refill handler
  calls, as result it runs much longer.

(https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html)

Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992
Reported-by: Victor Kamensky <kamensky@cisco.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201016133317.553068-1-f4bug@amsat.org>


  Commit: 22d30b340aa5d8a2b1fbc90d5263f801f1584d01
      
https://github.com/qemu/qemu/commit/22d30b340aa5d8a2b1fbc90d5263f801f1584d01
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-10-19 (Mon, 19 Oct 2020)

  Changed paths:
    M MAINTAINERS
    M docs/system/cpu-models-mips.rst.inc
    M hw/core/clock.c
    M hw/core/qdev-clock.c
    M hw/mips/boston.c
    M hw/mips/cps.c
    M hw/mips/fuloong2e.c
    M hw/mips/jazz.c
    M hw/mips/malta.c
    M hw/mips/mipssim.c
    M hw/mips/r4k.c
    M include/hw/clock.h
    M include/hw/mips/cps.h
    M include/hw/mips/mips.h
    M include/qemu/cutils.h
    M target/mips/cp0_helper.c
    M target/mips/cp0_timer.c
    M target/mips/cpu.c
    M target/mips/cpu.h
    M target/mips/fpu_helper.c
    M target/mips/internal.h
    M target/mips/op_helper.c
    M target/mips/translate.c
    M target/mips/translate_init.c.inc
    M tests/acceptance/replay_kernel.py
    M util/cutils.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-next-20201017' 
into staging

MIPS patches queue

. Fix some comment spelling errors
. Demacro some TCG helpers
. Add loongson-ext lswc2/lsdc2 group of instructions
. Log unimplemented cache opcode
. Increase number of TLB entries on the 34Kf core
. Allow the CPU to use dynamic frequencies
. Calculate the CP0 timer period using the CPU frequency
. Set CPU frequency for each machine
. Fix Malta FPGA I/O region size
. Allow running qtests when ROM is missing
. Add record/replay acceptance tests
. Update MIPS CPU documentation
. MAINTAINERS updates

CI jobs results:
  https://gitlab.com/philmd/qemu/-/pipelines/203931842
  https://travis-ci.org/github/philmd/qemu/builds/736491461
  https://cirrus-ci.com/build/6272264062631936
  https://app.shippable.com/github/philmd/qemu/runs/886/summary/console

# gpg: Signature made Sat 17 Oct 2020 14:59:53 BST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" 
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/mips-next-20201017: (44 commits)
  target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)
  MAINTAINERS: Remove duplicated Malta test entries
  MAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton mail
  MAINTAINERS: Put myself forward for MIPS target
  MAINTAINERS: Remove myself
  docs/system: Update MIPS CPU documentation
  tests/acceptance: Add MIPS record/replay tests
  hw/mips: Remove exit(1) in case of missing ROM
  hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON
  hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)
  hw/mips: Simplify loading 64-bit ELF kernels
  hw/mips/malta: Use clearer qdev style
  hw/mips/malta: Move gt64120 related code together
  hw/mips/malta: Fix FPGA I/O region size
  target/mips/cpu: Display warning when CPU is used without input clock
  hw/mips/cps: Do not allow use without input clock
  hw/mips/malta: Set CPU frequency to 320 MHz
  hw/mips/boston: Set CPU frequency to 1 GHz
  hw/mips/cps: Expose input clock and connect it to CPU cores
  hw/mips/jazz: Correct CPU frequencies
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/782d7b30dd8e...22d30b340aa5
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