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[Qemu-commits] [qemu/qemu] 8cbd46: hw/cpu/a9mpcore: Verify the machine u
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 8cbd46: hw/cpu/a9mpcore: Verify the machine use Cortex-A9 ... |
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Date: |
Mon, 24 Aug 2020 07:00:40 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 8cbd4616226aaf0f64599c64162062f0ecc0fe9b
https://github.com/qemu/qemu/commit/8cbd4616226aaf0f64599c64162062f0ecc0fe9b
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/cpu/a9mpcore.c
Log Message:
-----------
hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores
The 'Cortex-A9MPCore internal peripheral' block can only be
used with Cortex A5 and A9 cores. As we don't model the A5
yet, simply check the machine cpu core is a Cortex A9. If
not return an error.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200709152337.15533-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1733837d7cdb207653a849a5f1fa78de878c6ac1
https://github.com/qemu/qemu/commit/1733837d7cdb207653a849a5f1fa78de878c6ac1
Author: Eric Auger <eric.auger@redhat.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/arm/smmu-common.c
Log Message:
-----------
hw/arm/smmu-common: Factorize some code in smmu_ptw_64()
Page and block PTE decoding can share some code. Let's
first handle table PTE and factorize some code shared by
page and block PTEs.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-2-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6808bca939b8722d98165319ba42366ca80de907
https://github.com/qemu/qemu/commit/6808bca939b8722d98165319ba42366ca80de907
Author: Eric Auger <eric.auger@redhat.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmuv3.c
M hw/arm/trace-events
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmu-common: Add IOTLB helpers
Add two helpers: one to lookup for a given IOTLB entry and
one to insert a new entry. We also move the tracing there.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-3-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 60a61f1b31fc03080aadb63c9b1006f8b1972adb
https://github.com/qemu/qemu/commit/60a61f1b31fc03080aadb63c9b1006f8b1972adb
Author: Eric Auger <eric.auger@redhat.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmu-internal.h
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmu: Introduce smmu_get_iotlb_key()
Introduce the smmu_get_iotlb_key() helper and the
SMMU_IOTLB_ASID() macro. Also move smmu_get_iotlb_key and
smmu_iotlb_key_hash in the IOTLB related code section.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-4-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a7550158556b7fc2f2baaecf9092499c6687b160
https://github.com/qemu/qemu/commit/a7550158556b7fc2f2baaecf9092499c6687b160
Author: Eric Auger <eric.auger@redhat.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmuv3.c
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value
Introduce a specialized SMMUTLBEntry to store the result of
the PTW and cache in the IOTLB. This structure extends the
generic IOMMUTLBEntry struct with the level of the entry and
the granule size.
Those latter will be useful when implementing range invalidation.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-5-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9e54dee71fcfaae69f87b8e1f51485a832266a39
https://github.com/qemu/qemu/commit/9e54dee71fcfaae69f87b8e1f51485a832266a39
Author: Eric Auger <eric.auger@redhat.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmu-internal.h
M hw/arm/smmuv3.c
M hw/arm/trace-events
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmu-common: Manage IOTLB block entries
At the moment each entry in the IOTLB corresponds to a page sized
mapping (4K, 16K or 64K), even if the page belongs to a mapped
block. In case of block mapping this unefficiently consumes IOTLB
entries.
Change the value of the entry so that it reflects the actual
mapping it belongs to (block or page start address and size).
Also the level/tg of the entry is encoded in the key. In subsequent
patches we will enable range invalidation. This latter is able
to provide the level/tg of the entry.
Encoding the level/tg directly in the key will allow to invalidate
using g_hash_table_remove() when num_pages equals to 1.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-6-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c0f9ef70377cfcbd0fa6559d5dc729a930d71b7c
https://github.com/qemu/qemu/commit/c0f9ef70377cfcbd0fa6559d5dc729a930d71b7c
Author: Eric Auger <eric.auger@redhat.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/arm/smmuv3.c
M hw/arm/trace-events
Log Message:
-----------
hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper
Let's introduce an helper for S1 IOVA range invalidation.
This will be used for NH_VA and NH_VAA commands. It decodes
the same fields, trace, calls the UNMAP notifiers and
invalidate the corresponding IOTLB entries.
At the moment, we do not support 3.2 range invalidation yet.
So it reduces to a single IOVA invalidation.
Note the leaf bit now is also decoded for the CMD_TLBI_NH_VAA
command. At the moment it is only used for tracing.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-7-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d52915616c059ed273caa2d496b58e5d215c5962
https://github.com/qemu/qemu/commit/d52915616c059ed273caa2d496b58e5d215c5962
Author: Eric Auger <eric.auger@redhat.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M hw/arm/trace-events
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmuv3: Get prepared for range invalidation
Enhance the smmu_iotlb_inv_iova() helper with range invalidation.
This uses the new fields passed in the NH_VA and NH_VAA commands:
the size of the range, the level and the granule.
As NH_VA and NH_VAA both use those fields, their decoding and
handling is factorized in a new smmuv3_s1_range_inval() helper.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-8-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f0ec277cd46c0c7b078cc6bc90201999bb0dcd0b
https://github.com/qemu/qemu/commit/f0ec277cd46c0c7b078cc6bc90201999bb0dcd0b
Author: Eric Auger <eric.auger@redhat.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/arm/smmuv3-internal.h
Log Message:
-----------
hw/arm/smmuv3: Fix IIDR offset
The SMMU IIDR register is at 0x018 offset.
Fixes: 10a83cb9887 ("hw/arm/smmuv3: Skeleton")
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-9-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5888f0ad12e40c8b079365593900df80b5c261bf
https://github.com/qemu/qemu/commit/5888f0ad12e40c8b079365593900df80b5c261bf
Author: Eric Auger <eric.auger@redhat.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support
Add the support for AIDR register. It currently advertises
SMMU V3.0 spec.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-10-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e7c3b9d9a0ddee7daa9b08bd14bd3ebbcf5f5cd3
https://github.com/qemu/qemu/commit/e7c3b9d9a0ddee7daa9b08bd14bd3ebbcf5f5cd3
Author: Eric Auger <eric.auger@redhat.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M hw/arm/trace-events
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support
HAD is a mandatory features with SMMUv3.1 if S1P is set, which is
our case. Other 3.1 mandatory features come with S2P which we don't
have.
So let's support HAD and advertise SMMUv3.1 support in AIDR.
HAD support allows the CD to disable hierarchical attributes, ie.
if the HAD0/1 bit is set, the APTable field of table descriptors
walked through TTB0/1 is ignored.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-11-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: de206dfd80412ed1cdfb70d43ad53c59a19361ab
https://github.com/qemu/qemu/commit/de206dfd80412ed1cdfb70d43ad53c59a19361ab
Author: Eric Auger <eric.auger@redhat.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation
Expose the RIL bit so that the guest driver uses range
invalidation. Although RIL is a 3.2 features, We let
the AIDR advertise SMMUv3.1 support as v3.x implementation
is allowed to implement features from v3.(x+1).
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-12-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ff9e157bdc5620ca860b871ce63bf918d6808aaf
https://github.com/qemu/qemu/commit/ff9e157bdc5620ca860b871ce63bf918d6808aaf
Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M MAINTAINERS
A docs/system/arm/xlnx-versal-virt.rst
M docs/system/target-arm.rst
Log Message:
-----------
docs/system/arm: Document the Xilinx Versal Virt board
Document the Xilinx Versal Virt board.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200803164749.301971-2-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7b4f933db865391a90a3b4518bb2050a83f2a873
https://github.com/qemu/qemu/commit/7b4f933db865391a90a3b4518bb2050a83f2a873
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Pull handling of XScale insns out of disas_coproc_insn()
At the moment we check for XScale/iwMMXt insns inside
disas_coproc_insn(): for CPUs with ARM_FEATURE_XSCALE all copro insns
with cp 0 or 1 are handled specially. This works, but is an odd
place for this check, because disas_coproc_insn() is called from both
the Arm and Thumb decoders but the XScale case never applies for
Thumb (all the XScale CPUs were ARMv5, which has only Thumb1, not
Thumb2 with the 32-bit coprocessor insn encodings). It also makes it
awkward to convert the real copro access insns to decodetree.
Move the identification of XScale out to its own function
which is only called from disas_arm_insn().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-2-peter.maydell@linaro.org
Commit: 19c23a9baafc91dd3881a7a4e9bf454e42d24e4e
https://github.com/qemu/qemu/commit/19c23a9baafc91dd3881a7a4e9bf454e42d24e4e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Separate decode from handling of coproc insns
As a prelude to making coproc insns use decodetree, split out the
part of disas_coproc_insn() which does instruction decoding from the
part which does the actual work, and make do_coproc_insn() handle the
UNDEF-on-bad-permissions and similar cases itself rather than
returning 1 to eventually percolate up to a callsite that calls
unallocated_encoding() for it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-3-peter.maydell@linaro.org
Commit: cd8be50e58f63413c033531d3273c0e44851684f
https://github.com/qemu/qemu/commit/cd8be50e58f63413c033531d3273c0e44851684f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/a32.decode
M target/arm/helper.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert A32 coprocessor insns to decodetree
Convert the A32 coprocessor instructions to decodetree.
Note that this corrects an underdecoding: for the 64-bit access case
(MRRC/MCRR) we did not check that bits [24:21] were 0b0010, so we
would incorrectly treat LDC/STC as MRRC/MCRR rather than UNDEFing
them.
The decodetree versions of these insns assume the coprocessor
is in the range 0..7 or 14..15. This is architecturally sensible
(as per the comments) and OK in practice for QEMU because the only
uses of the ARMCPRegInfo infrastructure we have that aren't
for coprocessors 14 or 15 are the pxa2xx use of coprocessor 6.
We add an assertion to the define_one_arm_cp_reg_with_opaque()
function to catch any accidental future attempts to use it to
define coprocessor registers for invalid coprocessors.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-4-peter.maydell@linaro.org
Commit: 8198c071bc55bee55ef4f104a5b125f541b51096
https://github.com/qemu/qemu/commit/8198c071bc55bee55ef4f104a5b125f541b51096
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Tidy up disas_arm_insn()
The only thing left in the "legacy decoder" is the handling
of disas_xscale_insn(), and we can simplify the code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-5-peter.maydell@linaro.org
Commit: a3494d4671797c291c88bd414acb0aead15f7239
https://github.com/qemu/qemu/commit/a3494d4671797c291c88bd414acb0aead15f7239
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
A target/arm/m-nocp.decode
M target/arm/meson.build
M target/arm/translate-vfp.c.inc
M target/arm/translate.c
M target/arm/vfp.decode
Log Message:
-----------
target/arm: Do M-profile NOCP checks early and via decodetree
For M-profile CPUs, the architecture specifies that the NOCP
exception when a coprocessor is not present or disabled should cover
the entire wide range of coprocessor-space encodings, and should take
precedence over UNDEF exceptions. (This is the opposite of
A-profile, where checking for a disabled FPU has to happen last.)
Implement this with decodetree patterns that cover the specified
ranges of the encoding space. There are a few instructions (VLLDM,
VLSTM, and in v8.1 also VSCCLRM) which are in copro-space but must
not be NOCP'd: these must be handled also in the new m-nocp.decode so
they take precedence.
This is a minor behaviour change: for unallocated insn patterns in
the VFP area (cp=10,11) we will now NOCP rather than UNDEF when the
FPU is disabled.
As well as giving us the correct architectural behaviour for v8.1M
and the recommended behaviour for v8.0M, this refactoring also
removes the old NOCP handling from the remains of the 'legacy
decoder' in disas_thumb2_insn(), paving the way for cleaning that up.
Since we don't currently have a v8.1M feature bit or any v8.1M CPUs,
the minor changes to this logic that we'll need for v8.1M are marked
up with TODO comments.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-6-peter.maydell@linaro.org
Commit: 4c498dcfd84281f20bd55072630027d1b3c115fd
https://github.com/qemu/qemu/commit/4c498dcfd84281f20bd55072630027d1b3c115fd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/t32.decode
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert T32 coprocessor insns to decodetree
Convert the T32 coprocessor instructions to decodetree.
As with the A32 conversion, this corrects an underdecoding
where we did not check that MRRC/MCRR [24:21] were 0b0010
and so treated some kinds of LDC/STC and MRRC/MCRR rather
than UNDEFing them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-7-peter.maydell@linaro.org
Commit: ce51c7f522ca488c795c3510413e338021141c96
https://github.com/qemu/qemu/commit/ce51c7f522ca488c795c3510413e338021141c96
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Remove ARCH macro
The ARCH() macro was used a lot in the legacy decoder, but
there are now just two uses of it left. Since a macro which
expands out to a goto is liable to be confusing when reading
code, replace the last two uses with a simple open-coded
qeuivalent.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-8-peter.maydell@linaro.org
Commit: e60527c5d501e5015a119a0388a27abeae4dac09
https://github.com/qemu/qemu/commit/e60527c5d501e5015a119a0388a27abeae4dac09
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Delete unused VFP_DREG macros
As part of the Neon decodetree conversion we removed all
the uses of the VFP_DREG macros, but forgot to remove the
macro definitions. Do so now.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200803124848.18295-1-peter.maydell@linaro.org
Commit: 8b4c9a50dc9531a729ae4b5941d287ad0422db48
https://github.com/qemu/qemu/commit/8b4c9a50dc9531a729ae4b5941d287ad0422db48
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm/translate.c: Delete/amend incorrect comments
In arm_tr_init_disas_context() we have a FIXME comment that suggests
"cpu_M0 can probably be the same as cpu_V0". This isn't in fact
possible: cpu_V0 is used as a temporary inside gen_iwmmxt_shift(),
and that function is called in various places where cpu_M0 contains a
live value (i.e. between gen_op_iwmmxt_movq_M0_wRn() and
gen_op_iwmmxt_movq_wRn_M0() calls). Remove the comment.
We also have a comment on the declarations of cpu_V0/V1/M0 which
claims they're "for efficiency". This isn't true with modern TCG, so
replace this comment with one which notes that they're only used with
the iwmmxt decode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803132815.3861-1-peter.maydell@linaro.org
Commit: cf6303d262e31f4812dfeb654c6c6803e52000af
https://github.com/qemu/qemu/commit/cf6303d262e31f4812dfeb654c6c6803e52000af
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Delete unused ARM_FEATURE_CRC
In commit 962fcbf2efe57231a9f5df we converted the uses of the
ARM_FEATURE_CRC bit to use the aa32_crc32 isar_feature test
instead. However we forgot to remove the now-unused definition
of the feature name in the enum. Delete it now.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200805210848.6688-1-peter.maydell@linaro.org
Commit: cdfb22bb7326fee607d9553358856cca341dbc9a
https://github.com/qemu/qemu/commit/cdfb22bb7326fee607d9553358856cca341dbc9a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/translate-a64.c
M target/arm/translate-a64.h
M target/arm/translate-sve.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr()
We currently have two versions of get_fpstatus_ptr(), which both take
an effectively boolean argument:
* the one for A64 takes "bool is_f16" to distinguish fp16 from other ops
* the one for A32/T32 takes "int neon" to distinguish Neon from other ops
This is confusing, and to implement ARMv8.2-FP16 the A32/T32 one will
need to make a four-way distinction between "non-Neon, FP16",
"non-Neon, single/double", "Neon, FP16" and "Neon, single/double".
The A64 version will then be a strict subset of the A32/T32 version.
To clean this all up, we want to go to a single implementation which
takes an enum argument with values FPST_FPCR, FPST_STD,
FPST_FPCR_F16, and FPST_STD_F16. We rename the function to
fpstatus_ptr() so that unconverted code gets a compilation error
rather than silently passing the wrong thing to the new function.
This commit implements that new API, and converts A64 to use it:
get_fpstatus_ptr(false) -> fpstatus_ptr(FPST_FPCR)
get_fpstatus_ptr(true) -> fpstatus_ptr(FPST_FPCR_F16)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200806104453.30393-2-peter.maydell@linaro.org
Commit: a84d1d1316726704edd2617b2c30c921d98a8137
https://github.com/qemu/qemu/commit/a84d1d1316726704edd2617b2c30c921d98a8137
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/translate-neon.c.inc
M target/arm/translate-vfp.c.inc
M target/arm/translate.c
Log Message:
-----------
target/arm: Make A32/T32 use new fpstatus_ptr() API
Make A32/T32 code use the new fpstatus_ptr() API:
get_fpstatus_ptr(0) -> fpstatus_ptr(FPST_FPCR)
get_fpstatus_ptr(1) -> fpstatus_ptr(FPST_STD)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200806104453.30393-3-peter.maydell@linaro.org
Commit: aaae563bc73de0598bbc09a102e68f27fafe704a
https://github.com/qemu/qemu/commit/aaae563bc73de0598bbc09a102e68f27fafe704a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/translate.h
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Implement FPST_STD_F16 fpstatus
Architecturally, Neon FP16 operations use the "standard FPSCR" like
all other Neon operations. However, this is defined in the Arm ARM
pseudocode as "a fixed value, except that FZ16 (and AHP) follow the
FPSCR bits". In QEMU, the softfloat float_status doesn't include
separate flush-to-zero for FP16 operations, so we must keep separate
fp_status for "Neon non-FP16" and "Neon fp16" operations, in the
same way we do already for the non-Neon "fp_status" vs "fp_status_f16".
Add the extra float_status field to the CPU state structure,
ensure it is correctly initialized and updated on FPSCR writes,
and make fpstatus_ptr(FPST_STD_F16) return a pointer to it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200806104453.30393-4-peter.maydell@linaro.org
Commit: b34aa5129e9c3aff890b4f4bcc84962e94185629
https://github.com/qemu/qemu/commit/b34aa5129e9c3aff890b4f4bcc84962e94185629
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M target/arm/translate-neon.c.inc
Log Message:
-----------
target/arm: Use correct FPST for VCMLA, VCADD on fp16
When we implemented the VCMLA and VCADD insns we put in the
code to handle fp16, but left it using the standard fp status
flags. Correct them to use FPST_STD_F16 for fp16 operations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200806104453.30393-5-peter.maydell@linaro.org
Commit: 07d914cb9489f7acbd91ed675355674c8a5545b0
https://github.com/qemu/qemu/commit/07d914cb9489f7acbd91ed675355674c8a5545b0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-08-24 (Mon, 24 Aug 2020)
Changed paths:
M MAINTAINERS
A docs/system/arm/xlnx-versal-virt.rst
M docs/system/target-arm.rst
M hw/arm/smmu-common.c
M hw/arm/smmu-internal.h
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M hw/arm/trace-events
M hw/cpu/a9mpcore.c
M include/hw/arm/smmu-common.h
M include/hw/arm/smmuv3.h
M target/arm/a32.decode
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
A target/arm/m-nocp.decode
M target/arm/meson.build
M target/arm/t32.decode
M target/arm/translate-a64.c
M target/arm/translate-a64.h
M target/arm/translate-neon.c.inc
M target/arm/translate-sve.c
M target/arm/translate-vfp.c.inc
M target/arm/translate.c
M target/arm/translate.h
M target/arm/vfp.decode
M target/arm/vfp_helper.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200824'
into staging
target-arm queue:
* hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores
* hw/arm/smmuv3: Implement SMMUv3.2 range-invalidation
* docs/system/arm: Document the Xilinx Versal Virt board
* target/arm: Make M-profile NOCP take precedence over UNDEF
* target/arm: Use correct FPST for VCMLA, VCADD on fp16
* target/arm: Various cleanups preparing for fp16 support
# gpg: Signature made Mon 24 Aug 2020 10:47:14 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200824: (27 commits)
target/arm: Use correct FPST for VCMLA, VCADD on fp16
target/arm: Implement FPST_STD_F16 fpstatus
target/arm: Make A32/T32 use new fpstatus_ptr() API
target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr()
target/arm: Delete unused ARM_FEATURE_CRC
target/arm/translate.c: Delete/amend incorrect comments
target/arm: Delete unused VFP_DREG macros
target/arm: Remove ARCH macro
target/arm: Convert T32 coprocessor insns to decodetree
target/arm: Do M-profile NOCP checks early and via decodetree
target/arm: Tidy up disas_arm_insn()
target/arm: Convert A32 coprocessor insns to decodetree
target/arm: Separate decode from handling of coproc insns
target/arm: Pull handling of XScale insns out of disas_coproc_insn()
docs/system/arm: Document the Xilinx Versal Virt board
hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation
hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support
hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support
hw/arm/smmuv3: Fix IIDR offset
hw/arm/smmuv3: Get prepared for range invalidation
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/dd8014e4e904...07d914cb9489
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