[Qemu-commits] [qemu/qemu] aa4d30: riscv: plic: Honour source priorities

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[Qemu-commits] [qemu/qemu] aa4d30: riscv: plic: Honour source priorities

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] aa4d30: riscv: plic: Honour source priorities
Date:	Fri, 03 Jul 2020 10:00:27 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: aa4d30f6618dcaf033c4294ca219ef17a6bae69f
      
https://github.com/qemu/qemu/commit/aa4d30f6618dcaf033c4294ca219ef17a6bae69f
  Author: Jessica Clarke <jrtc27@jrtc27.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M hw/riscv/sifive_plic.c

  Log Message:
  -----------
  riscv: plic: Honour source priorities

The source priorities can be used to order sources with respect to other
sources, not just as a way to enable/disable them based off a threshold.
We must therefore always claim the highest-priority source, rather than
the first source we find.

Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200618202343.20455-1-jrtc27@jrtc27.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 55765822804f5a58594e0931e0fb8f80337b5425
      
https://github.com/qemu/qemu/commit/55765822804f5a58594e0931e0fb8f80337b5425
  Author: Jessica Clarke <jrtc27@jrtc27.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M hw/riscv/sifive_plic.c

  Log Message:
  -----------
  riscv: plic: Add a couple of mising sifive_plic_update calls

Claiming an interrupt and changing the source priority both potentially
affect whether an interrupt is pending, thus we must re-compute xEIP.
Note that we don't put the sifive_plic_update inside sifive_plic_claim
so that the logging of a claim (and the resulting IRQ) happens before
the state update, making the causal effect clear, and that we drop the
explicit call to sifive_plic_print_state when claiming since
sifive_plic_update already does that automatically at the end for us.

This can result in both spurious interrupt storms if you fail to
complete an IRQ before enabling interrupts (and no other actions occur
that result in a call to sifive_plic_update), but also more importantly
lost interrupts if a disabled interrupt is pending and then becomes
enabled.

Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200618210649.22451-1-jrtc27@jrtc27.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 70b78d4e71494c90d2ccb40381336bc9b9a22f79
      
https://github.com/qemu/qemu/commit/70b78d4e71494c90d2ccb40381336bc9b9a22f79
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M hw/riscv/sifive_clint.c

  Log Message:
  -----------
  hw/riscv: Allow 64 bit access to SiFive CLINT

Commit 5d971f9e672507210e77d020d89e0e89165c8fc9
"memory: Revert "memory: accept mismatching sizes in
memory_region_access_valid"" broke most RISC-V boards as they do 64 bit
accesses to the CLINT and QEMU would trigger a fault. Fix this failure
by allowing 8 byte accesses.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Message-Id: 
<122b78825b077e4dfd39b444d3a46fe894a7804c.1593547870.git.alistair.francis@wdc.com>


  Commit: ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0
      
https://github.com/qemu/qemu/commit/ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: add vector extension field in CPURISCVState

The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-2-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 32931383270e2ca8209267ca99f23f3c5f780982
      
https://github.com/qemu/qemu/commit/32931383270e2ca8209267ca99f23f3c5f780982
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: implementation-defined constant parameters

vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-3-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8e3a1f18871e0ea251b95561fe1ec5a9bc896c4a
      
https://github.com/qemu/qemu/commit/8e3a1f18871e0ea251b95561fe1ec5a9bc896c4a
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: support vector extension csr

The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-4-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2b7168fc43fb270fb89e1dddc17ef54714712f3a
      
https://github.com/qemu/qemu/commit/2b7168fc43fb270fb89e1dddc17ef54714712f3a
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/Makefile.objs
    M target/riscv/cpu.h
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/translate.c
    A target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: add vector configure instruction

vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-5-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f476f17740ad42288d42dd8fedcdae8ca7007a16
      
https://github.com/qemu/qemu/commit/f476f17740ad42288d42dd8fedcdae8ca7007a16
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    A target/riscv/internals.h

  Log Message:
  -----------
  target/riscv: add an internals.h header

The internals.h keeps things that are not relevant to the actual architecture,
only to the implementation, separate.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-6-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 751538d5da557e5c10e5045c2d27639580ea54a7
      
https://github.com/qemu/qemu/commit/751538d5da557e5c10e5045c2d27639580ea54a7
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/internals.h
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: add vector stride load and store instructions

Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.

Vector unit-stride operations access elements stored contiguously in memory
starting from the base effective address. It can been seen as a special
case of strided operations.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f732560e3551c0823cee52efba993fbb8f689a36
      
https://github.com/qemu/qemu/commit/f732560e3551c0823cee52efba993fbb8f689a36
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: add vector index load and store instructions

Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-8-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 022b4ecf775ffeff522eaea4f0d94edcfe00a0a9
      
https://github.com/qemu/qemu/commit/022b4ecf775ffeff522eaea4f0d94edcfe00a0a9
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: add fault-only-first unit stride load

The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-9-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 268fcca66bde62257960ec8d859de374315a5e3d
      
https://github.com/qemu/qemu/commit/268fcca66bde62257960ec8d859de374315a5e3d
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32-64.decode
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/internals.h
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: add vector amo operations

Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-10-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 43740e3a3b3bb66456103684e622ba4e9baae297
      
https://github.com/qemu/qemu/commit/43740e3a3b3bb66456103684e622ba4e9baae297
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width integer add and subtract

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-11-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8fcdf77630290591a6068c2d82ca2935338c3b0c
      
https://github.com/qemu/qemu/commit/8fcdf77630290591a6068c2d82ca2935338c3b0c
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector widening integer add and subtract

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-12-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3a6f8f68ad2f4a22d9ae8287f336b5dcc80b6448
      
https://github.com/qemu/qemu/commit/3a6f8f68ad2f4a22d9ae8287f336b5dcc80b6448
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector integer add-with-carry / subtract-with-borrow 
instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-13-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d3842924cf93d104f691c5ea9090d6700ccef281
      
https://github.com/qemu/qemu/commit/d3842924cf93d104f691c5ea9090d6700ccef281
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector bitwise logical instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-14-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3277d955d21d8943d80062b4cfd8547f831dbd51
      
https://github.com/qemu/qemu/commit/3277d955d21d8943d80062b4cfd8547f831dbd51
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width bit shift instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-15-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7689b028ca56268fde3d492038413582b494c489
      
https://github.com/qemu/qemu/commit/7689b028ca56268fde3d492038413582b494c489
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector narrowing integer right shift instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-16-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1366fc79be04fa56a0e3f078ba4f26c27ac67e89
      
https://github.com/qemu/qemu/commit/1366fc79be04fa56a0e3f078ba4f26c27ac67e89
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector integer comparison instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-17-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 558fa7797c919c4f21ac10980f3ed28160d6d3cb
      
https://github.com/qemu/qemu/commit/558fa7797c919c4f21ac10980f3ed28160d6d3cb
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector integer min/max instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-18-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 958b85f3686631af93f695b2a5dd047e037074f2
      
https://github.com/qemu/qemu/commit/958b85f3686631af93f695b2a5dd047e037074f2
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width integer multiply instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-19-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 85e6658cfe9d71cc207a710ffdf0e6546f8612aa
      
https://github.com/qemu/qemu/commit/85e6658cfe9d71cc207a710ffdf0e6546f8612aa
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector integer divide instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-20-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 97b1cba39967251ab78b9d52fd9a4c62bb42d428
      
https://github.com/qemu/qemu/commit/97b1cba39967251ab78b9d52fd9a4c62bb42d428
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector widening integer multiply instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-21-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 54df813a331d3badfb83604c36bef7cb1de4315a
      
https://github.com/qemu/qemu/commit/54df813a331d3badfb83604c36bef7cb1de4315a
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width integer multiply-add instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-22-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2b587b335050dbc0cb3823758341f145c0375312
      
https://github.com/qemu/qemu/commit/2b587b335050dbc0cb3823758341f145c0375312
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector widening integer multiply-add instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-23-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f020a7a14505d6996497693e63331ab609847d93
      
https://github.com/qemu/qemu/commit/f020a7a14505d6996497693e63331ab609847d93
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector integer merge and move instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-24-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: eb2650e35ec1ed60ff302ce3330bd6c770640833
      
https://github.com/qemu/qemu/commit/eb2650e35ec1ed60ff302ce3330bd6c770640833
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width saturating add and subtract

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-25-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b7aee4819206cbb7adfdb624d4f2fa9918c25d43
      
https://github.com/qemu/qemu/commit/b7aee4819206cbb7adfdb624d4f2fa9918c25d43
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width averaging add and subtract

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-26-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9f0ff9e51480f8f1d2d7a62b11aa156fcdb4ef95
      
https://github.com/qemu/qemu/commit/9f0ff9e51480f8f1d2d7a62b11aa156fcdb4ef95
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width fractional multiply with rounding and 
saturation

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-27-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0a1eaf0036442b2bfa69df7fad9a5f1d6a4984f2
      
https://github.com/qemu/qemu/commit/0a1eaf0036442b2bfa69df7fad9a5f1d6a4984f2
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector widening saturating scaled multiply-add

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-28-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 04a614062dd5fb43f00bd955f44f7a2c3def016d
      
https://github.com/qemu/qemu/commit/04a614062dd5fb43f00bd955f44f7a2c3def016d
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width scaling shift instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-29-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9ff3d28739b760970f5e542c74a033470dca3f9b
      
https://github.com/qemu/qemu/commit/9ff3d28739b760970f5e542c74a033470dca3f9b
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector narrowing fixed-point clip instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-30-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ce2a0343f441f0ee949690eabae5ab600397e2eb
      
https://github.com/qemu/qemu/commit/ce2a0343f441f0ee949690eabae5ab600397e2eb
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-31-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: eeffab2ec1b332a5eb2d2dcd2732cdb57179c6eb
      
https://github.com/qemu/qemu/commit/eeffab2ec1b332a5eb2d2dcd2732cdb57179c6eb
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector widening floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-32-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0e0057cbe2169195a08ae8247504e69f9b80542b
      
https://github.com/qemu/qemu/commit/0e0057cbe2169195a08ae8247504e69f9b80542b
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width floating-point multiply/divide instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-33-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f7c7b7cd293ca6f14f23cc2c14d6d23fc47a604d
      
https://github.com/qemu/qemu/commit/f7c7b7cd293ca6f14f23cc2c14d6d23fc47a604d
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector widening floating-point multiply

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-34-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4aa5a8fed4a21fe2e132a9a21b251aa95e19de80
      
https://github.com/qemu/qemu/commit/4aa5a8fed4a21fe2e132a9a21b251aa95e19de80
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width floating-point fused multiply-add 
instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-35-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0dd509594fbd53fc9c3edc79bd7a575f079c3c87
      
https://github.com/qemu/qemu/commit/0dd509594fbd53fc9c3edc79bd7a575f079c3c87
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector widening floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-36-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d9e4ce72a5a0f7c404156d40d3252d4d6a9d6a36
      
https://github.com/qemu/qemu/commit/d9e4ce72a5a0f7c404156d40d3252d4d6a9d6a36
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector floating-point square-root instruction

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-37-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 230b53ddd706c8b18a6d9beed1a0153b276d7037
      
https://github.com/qemu/qemu/commit/230b53ddd706c8b18a6d9beed1a0153b276d7037
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector floating-point min/max instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-38-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1d426b81f71eeeb1cbfec76c2f27ed0495719fb0
      
https://github.com/qemu/qemu/commit/1d426b81f71eeeb1cbfec76c2f27ed0495719fb0
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector floating-point sign-injection instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-39-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2a68e9e568faddf4d689a37fa6895bcb8404a677
      
https://github.com/qemu/qemu/commit/2a68e9e568faddf4d689a37fa6895bcb8404a677
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector floating-point compare instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-40-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 121ddbb36f17d24a7f39d6024d9b3145d154a98c
      
https://github.com/qemu/qemu/commit/121ddbb36f17d24a7f39d6024d9b3145d154a98c
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/internals.h
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector floating-point classify instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-41-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 64ab5846974140118c64e4d94ff2696932a0a58b
      
https://github.com/qemu/qemu/commit/64ab5846974140118c64e4d94ff2696932a0a58b
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector floating-point merge instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-42-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 921009732614fd620c75f05496597796719544cf
      
https://github.com/qemu/qemu/commit/921009732614fd620c75f05496597796719544cf
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-43-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4514b7b12390525e59e335e7ca58fd44f6e69272
      
https://github.com/qemu/qemu/commit/4514b7b12390525e59e335e7ca58fd44f6e69272
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: widening floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-44-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 878d406ec28f945d262af4ffbea50b825d7a0825
      
https://github.com/qemu/qemu/commit/878d406ec28f945d262af4ffbea50b825d7a0825
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: narrowing floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-45-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: fe5c9ab1fc185e96bf7e034954127429ca74d386
      
https://github.com/qemu/qemu/commit/fe5c9ab1fc185e96bf7e034954127429ca74d386
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width integer reduction instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-46-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bba718200b2d2aac6ab5031817f7125571c983a1
      
https://github.com/qemu/qemu/commit/bba718200b2d2aac6ab5031817f7125571c983a1
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector wideing integer reduction instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-47-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 523547f19e3914f11543e2da03907c724f15cd5e
      
https://github.com/qemu/qemu/commit/523547f19e3914f11543e2da03907c724f15cd5e
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector single-width floating-point reduction instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-48-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 696b0c260a0312c865cd0e4a8f09d0b9f13b07c9
      
https://github.com/qemu/qemu/commit/696b0c260a0312c865cd0e4a8f09d0b9f13b07c9
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector widening floating-point reduction instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-49-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c21f34aebfb15c112131e36f425986170a3fcae9
      
https://github.com/qemu/qemu/commit/c21f34aebfb15c112131e36f425986170a3fcae9
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector mask-register logical instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-50-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2e88f551df8fe6af81c0f920b7341ae2c75d00f2
      
https://github.com/qemu/qemu/commit/2e88f551df8fe6af81c0f920b7341ae2c75d00f2
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector mask population count vmpopc

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-51-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0db67e1c0c49011eb09c4f5b790eef15a2b4c351
      
https://github.com/qemu/qemu/commit/0db67e1c0c49011eb09c4f5b790eef15a2b4c351
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vmfirst find-first-set mask bit

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-52-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 81fbf7daf2eccadd6480b90db95a2e8c410d4414
      
https://github.com/qemu/qemu/commit/81fbf7daf2eccadd6480b90db95a2e8c410d4414
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: set-X-first mask bit

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-53-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 78d90cfe859c8f5bd7baa0d41a4b5126e08eac24
      
https://github.com/qemu/qemu/commit/78d90cfe859c8f5bd7baa0d41a4b5126e08eac24
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector iota instruction

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-54-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 126bec3f6ff3379e1a49f4a7d36922bfd079a3cc
      
https://github.com/qemu/qemu/commit/126bec3f6ff3379e1a49f4a7d36922bfd079a3cc
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector element index instruction

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-55-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 90355f391d979ccd95d09ab42f647f103a3dbe69
      
https://github.com/qemu/qemu/commit/90355f391d979ccd95d09ab42f647f103a3dbe69
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c

  Log Message:
  -----------
  target/riscv: integer extract instruction

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-56-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9fc08be626a96ae1ac0cffb22f30ae652c1c645a
      
https://github.com/qemu/qemu/commit/9fc08be626a96ae1ac0cffb22f30ae652c1c645a
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/internals.h

  Log Message:
  -----------
  target/riscv: integer scalar move instruction

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-57-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2843420a562c107801bae20f74579e4fe540316f
      
https://github.com/qemu/qemu/commit/2843420a562c107801bae20f74579e4fe540316f
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c

  Log Message:
  -----------
  target/riscv: floating-point scalar move instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-58-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ec17e03688ce4d0ae188db6d90b185b92a9a2087
      
https://github.com/qemu/qemu/commit/ec17e03688ce4d0ae188db6d90b185b92a9a2087
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector slide instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-59-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e4b83d5c0928507cc27a0f613675b117db9993e4
      
https://github.com/qemu/qemu/commit/e4b83d5c0928507cc27a0f613675b117db9993e4
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector register gather instruction

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-60-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 31bf42a26cf8b1e02f27acd302ee0ef14e877682
      
https://github.com/qemu/qemu/commit/31bf42a26cf8b1e02f27acd302ee0ef14e877682
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: vector compress instruction

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-61-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6bf91617f47c74efc99ef48236765d9677c0898e
      
https://github.com/qemu/qemu/commit/6bf91617f47c74efc99ef48236765d9677c0898e
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-02 (Thu, 02 Jul 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: configure and turn on vector extension from command line

Vector extension is default off. The only way to use vector extension is
1. use cpu rv32 or rv64
2. turn on it by command line
   "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1".

vlen is the vector register length, default value is 128 bit.
elen is the max operator size in bits, default value is 64 bit.
vext_spec is the vector specification version, default value is v0.7.1.
These properties can be specified with other values.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-62-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5f42c3375d45108cf14f50ac8ba57c2865e75e9c
      
https://github.com/qemu/qemu/commit/5f42c3375d45108cf14f50ac8ba57c2865e75e9c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-07-03 (Fri, 03 Jul 2020)

  Changed paths:
    M hw/riscv/sifive_clint.c
    M hw/riscv/sifive_plic.c
    M target/riscv/Makefile.objs
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c
    M target/riscv/fpu_helper.c
    M target/riscv/helper.h
    M target/riscv/insn32-64.decode
    M target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_rvv.inc.c
    A target/riscv/internals.h
    M target/riscv/translate.c
    A target/riscv/vector_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20200702-1' into staging

This PR contains two patches to improve PLIC support in QEMU.

It also contains one patch that fixes CLINT accesses for RISC-V. This
fixes a regression for most RISC-V boards.

The rest of the PR is adding support for the v0.7.1 RISC-V vector
extensions. This is experimental support as the vector extensions are
still in a draft state.

This is a v2 pull request that has fixed the building on big endian
machines failure.

# gpg: Signature made Thu 02 Jul 2020 17:21:54 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200702-1: (64 commits)
  target/riscv: configure and turn on vector extension from command line
  target/riscv: vector compress instruction
  target/riscv: vector register gather instruction
  target/riscv: vector slide instructions
  target/riscv: floating-point scalar move instructions
  target/riscv: integer scalar move instruction
  target/riscv: integer extract instruction
  target/riscv: vector element index instruction
  target/riscv: vector iota instruction
  target/riscv: set-X-first mask bit
  target/riscv: vmfirst find-first-set mask bit
  target/riscv: vector mask population count vmpopc
  target/riscv: vector mask-register logical instructions
  target/riscv: vector widening floating-point reduction instructions
  target/riscv: vector single-width floating-point reduction instructions
  target/riscv: vector wideing integer reduction instructions
  target/riscv: vector single-width integer reduction instructions
  target/riscv: narrowing floating-point/integer type-convert instructions
  target/riscv: widening floating-point/integer type-convert instructions
  target/riscv: vector floating-point/integer type-convert instructions
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/4abf70a661a5...5f42c3375d45
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