[Qemu-commits] [qemu/qemu] c62288: hw/arm/virt: Add 5.0 HW compat props

qemu-commits
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] c62288: hw/arm/virt: Add 5.0 HW compat props

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] c62288: hw/arm/virt: Add 5.0 HW compat props
Date:	Wed, 24 Jun 2020 13:15:29 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: c62288072c9c6c275a28c074612941a44572691d
      
https://github.com/qemu/qemu/commit/c62288072c9c6c275a28c074612941a44572691d
  Author: Andrew Jones <drjones@redhat.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Add 5.0 HW compat props

Cc: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20200616140803.25515-1-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2032e243a52c9834e5536463bcaa179f18d3319f
      
https://github.com/qemu/qemu/commit/2032e243a52c9834e5536463bcaa179f18d3319f
  Author: David CARLIER <devnexen@gmail.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M util/oslib-posix.c

  Log Message:
  -----------
  util/oslib-posix : qemu_init_exec_dir implementation for Mac

>From 3025a0ce3fdf7d3559fc35a52c659f635f5c750c Mon Sep 17 00:00:00 2001
From: David Carlier <devnexen@gmail.com>
Date: Tue, 26 May 2020 21:35:27 +0100
Subject: [PATCH] util/oslib-posix : qemu_init_exec_dir implementation for Mac

Using dyld API to get the full path of the current process.

Signed-off-by: David Carlier <devnexen@gmail.com>
Message-id: CA+XhMqxwC10XHVs4Z-JfE0-WLAU3ztDuU9QKVi31mjr59HWCxg@mail.gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 353d2b85058711a5e44c2dc63eb5b620db50a602
      
https://github.com/qemu/qemu/commit/353d2b85058711a5e44c2dc63eb5b620db50a602
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-misc VREV64 to decodetree

Convert the Neon VREV64 insn from the 2-reg-misc grouping to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-2-peter.maydell@linaro.org


  Commit: 6106af3aa2304fccee91a3a90138352b0c2af998
      
https://github.com/qemu/qemu/commit/6106af3aa2304fccee91a3a90138352b0c2af998
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-misc pairwise ops to decodetree

Convert the pairwise ops VPADDL and VPADAL in the 2-reg-misc grouping
to decodetree.

At this point we can get rid of the weird CPU_V001 #define that was
used to avoid having to explicitly list all the arguments being
passed to some TCG gen/helper functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-3-peter.maydell@linaro.org


  Commit: 567663a2af2457da8aa74f221b1f3f8a6d2eddf6
      
https://github.com/qemu/qemu/commit/567663a2af2457da8aa74f221b1f3f8a6d2eddf6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert VZIP, VUZP to decodetree

Convert the Neon VZIP and VUZP insns in the 2-reg-misc group to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-4-peter.maydell@linaro.org


  Commit: 3882bdacb0ad548864b9f2582a32bb5c785e3165
      
https://github.com/qemu/qemu/commit/3882bdacb0ad548864b9f2582a32bb5c785e3165
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon narrowing moves to decodetree

Convert the Neon narrowing moves VMQNV, VQMOVN, VQMOVUN in the 2-reg-misc
group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-5-peter.maydell@linaro.org


  Commit: 749e2be36d75f11d5fa8f8277e2a0569bd2a1c97
      
https://github.com/qemu/qemu/commit/749e2be36d75f11d5fa8f8277e2a0569bd2a1c97
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-misc VSHLL to decodetree

Convert the VSHLL insn in the 2-reg-misc Neon group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-6-peter.maydell@linaro.org


  Commit: 654a517355e249435505ae5ff14a7520410cf7a4
      
https://github.com/qemu/qemu/commit/654a517355e249435505ae5ff14a7520410cf7a4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VCVT f16/f32 insns to decodetree

Convert the Neon insns in the 2-reg-misc group which are
VCVT between f32 and f16 to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-7-peter.maydell@linaro.org


  Commit: 75153179e9928775d5333243ea4b278f438d75ae
      
https://github.com/qemu/qemu/commit/75153179e9928775d5333243ea4b278f438d75ae
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert vectorised 2-reg-misc Neon ops to decodetree

Convert to decodetree the insns in the Neon 2-reg-misc grouping which
we implement using gvec.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-8-peter.maydell@linaro.org


  Commit: 0b30dd5b85e20aba259768cb7aaa952b3e319468
      
https://github.com/qemu/qemu/commit/0b30dd5b85e20aba259768cb7aaa952b3e319468
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-misc crypto operations to decodetree

Convert the Neon-2-reg misc crypto ops (AESE, AESMC, SHA1H, SHA1SU1)
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-9-peter.maydell@linaro.org


  Commit: 039f4e809ad2772fb33de4511ff68a485d875618
      
https://github.com/qemu/qemu/commit/039f4e809ad2772fb33de4511ff68a485d875618
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFn

The NeonGenOneOpFn typedef breaks with the pattern of the other
NeonGen*Fn typedefs, because it is a TCGv_i64 -> TCGv_i64 operation
but it does not have '64' in its name. Rename it to NeonGenOne64OpFn,
so that the old name is available for a TCGv_i32 -> TCGv_i32 operation
(which we will need in a subsequent commit).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-10-peter.maydell@linaro.org


  Commit: 5de3fd045be11b74cd0fbf36c6d4fb8387d5463b
      
https://github.com/qemu/qemu/commit/5de3fd045be11b74cd0fbf36c6d4fb8387d5463b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate-neon.inc.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefs

All the other typedefs like these spell "Op" with a lowercase 'p';
remane the NeonGenTwoSingleOPFn and NeonGenTwoDoubleOPFn typedefs to
match.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-11-peter.maydell@linaro.org


  Commit: 8ec3de7018a8198624aae49eef5568256114a829
      
https://github.com/qemu/qemu/commit/8ec3de7018a8198624aae49eef5568256114a829
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Make gen_swap_half() take separate src and dest

Make gen_swap_half() take a source and destination TCGv_i32 rather
than modifying the input TCGv_i32; we're going to want to be able to
use it with the more flexible function signature, and this also
brings it into line with other functions like gen_rev16() and
gen_revsh().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-12-peter.maydell@linaro.org


  Commit: 8966808205b59d6c196b380b638475bcd1657ef4
      
https://github.com/qemu/qemu/commit/8966808205b59d6c196b380b638475bcd1657ef4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree

Convert the VREV32 and VREV16 insns in the Neon 2-reg-misc group
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-13-peter.maydell@linaro.org


  Commit: 84eae770af69c37a92496a4c4248875c070d5ee3
      
https://github.com/qemu/qemu/commit/84eae770af69c37a92496a4c4248875c070d5ee3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert remaining simple 2-reg-misc Neon ops

Convert the remaining ops in the Neon 2-reg-misc group which
can be implemented simply with our do_2misc() helper.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-14-peter.maydell@linaro.org


  Commit: 4936f38abe6db0a9d23fd04e4cb0cf4d51cff174
      
https://github.com/qemu/qemu/commit/4936f38abe6db0a9d23fd04e4cb0cf4d51cff174
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VQABS, VQNEG to decodetree

Convert the Neon VQABS and VQNEG insns to decodetree.
Since these are the only ones which need cpu_env passing to
the helper, we wrap the helper rather than creating a whole
new do_2misc_env() function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-15-peter.maydell@linaro.org


  Commit: 3e96b205286dfb8bbf363229709e4f8648fce379
      
https://github.com/qemu/qemu/commit/3e96b205286dfb8bbf363229709e4f8648fce379
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Convert simple fp Neon 2-reg-misc insns

Convert the Neon 2-reg-misc insns which are implemented with
simple calls to functions that take the input, output and
fpstatus pointer.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-16-peter.maydell@linaro.org


  Commit: baa59323e841f76523f6ad4d746cdeb47ea574cd
      
https://github.com/qemu/qemu/commit/baa59323e841f76523f6ad4d746cdeb47ea574cd
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree

Convert the fp-compare-with-zero insns in the Neon 2-reg-misc group to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-17-peter.maydell@linaro.org


  Commit: 128123ea34e9e6afe4842aefcb9cf84b9642ac22
      
https://github.com/qemu/qemu/commit/128123ea34e9e6afe4842aefcb9cf84b9642ac22
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree

Convert the Neon 2-reg-misc VRINT insns to decodetree.
Giving these insns their own do_vrint() function allows us
to change the rounding mode just once at the start and end
rather than doing it for every element in the vector.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-18-peter.maydell@linaro.org


  Commit: a183d5fb38b07bab2a840196186c4806f3c67c0d
      
https://github.com/qemu/qemu/commit/a183d5fb38b07bab2a840196186c4806f3c67c0d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree

Convert the VCVT instructions in the 2-reg-misc grouping to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-19-peter.maydell@linaro.org


  Commit: 8ab3a227a0f13f0ff85846f36f7c466769aef4fc
      
https://github.com/qemu/qemu/commit/8ab3a227a0f13f0ff85846f36f7c466769aef4fc
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VSWP to decodetree

Convert the Neon VSWP insn to decodetree. Since the new implementation
doesn't have to share a pass-loop with the other 2-reg-misc operations
we can implement the swap with 64-bit accesses rather than 32-bits
(which brings us into line with the pseudocode and is more efficient).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-20-peter.maydell@linaro.org


  Commit: d4366190f84fe89cc5d46da995dac1e7d541b98e
      
https://github.com/qemu/qemu/commit/d4366190f84fe89cc5d46da995dac1e7d541b98e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VTRN to decodetree

Convert the Neon VTRN insn to decodetree. This is the last insn in the
Neon data-processing group, so we can remove all the now-unused old
decoder framework.

It's possible that there's a more efficient implementation of
VTRN, but for this conversion we just copy the existing approach.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-21-peter.maydell@linaro.org


  Commit: 6fb5787898aab6aa04887fed9cf3220dd4c3f36a
      
https://github.com/qemu/qemu/commit/6fb5787898aab6aa04887fed9cf3220dd4c3f36a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Move some functions used only in translate-neon.inc.c to that file

The functions neon_element_offset(), neon_load_element(),
neon_load_element64(), neon_store_element() and
neon_store_element64() are used only in the translate-neon.inc.c
file, so move their definitions there.

Since the .inc.c file is #included in translate.c this doesn't make
much difference currently, but it's a more logical place to put the
functions and it might be helpful if we ever decide to try to make
the .inc.c files genuinely separate compilation units.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-22-peter.maydell@linaro.org


  Commit: 55c812b74289863c348449135812027d188f040a
      
https://github.com/qemu/qemu/commit/55c812b74289863c348449135812027d188f040a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Remove unnecessary gen_io_end() calls

Since commit ba3e7926691ed3 it has been unnecessary for target code
to call gen_io_end() after an IO instruction in icount mode; it is
sufficient to call gen_io_start() before it and to force the end of
the TB.

Many now-unnecessary calls to gen_io_end() were removed in commit
9e9b10c6491153b, but some were missed or accidentally added later.
Remove unneeded calls from the arm target:

 * the call in the handling of exception-return-via-LDM is
   unnecessary, and the code is already forcing end-of-TB
 * the call in the VFP access check code is more complicated:
   we weren't ending the TB, so we need to add the code to
   force that by setting DISAS_UPDATE
 * the doc comment for ARM_CP_IO doesn't need to mention
   gen_io_end() any more

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
Message-id: 20200619170324.12093-1-peter.maydell@linaro.org


  Commit: ced7e8edb282765685d2ba0206a11f8692d8ec1c
      
https://github.com/qemu/qemu/commit/ced7e8edb282765685d2ba0206a11f8692d8ec1c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Remove dead code relating to SABA and UABA

In commit cfdb2c0c95ae9205b0 ("target/arm: Vectorize SABA/UABA") we
replaced the old handling of SABA/UABA with a vectorized implementation
which returns early rather than falling into the loop-ever-elements
code. We forgot to delete the part of the old looping code that
did the accumulate step, and Coverity correctly warns (CID 1428955)
that this code is now dead. Delete it.

Fixes: cfdb2c0c95ae9205b0
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200619171547.29780-1-peter.maydell@linaro.org


  Commit: 69ed08e4c5bb0b9d9ae55219ba5429064b0d272e
      
https://github.com/qemu/qemu/commit/69ed08e4c5bb0b9d9ae55219ba5429064b0d272e
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/watchdog/cmsdk-apb-watchdog.c
    M hw/watchdog/trace-events

  Log Message:
  -----------
  hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status

Add a trace event to see when a guest disable/enable the watchdog.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-2-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: faa1bdfa32547ea616ec554aa807b4e24e30acef
      
https://github.com/qemu/qemu/commit/faa1bdfa32547ea616ec554aa807b4e24e30acef
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/i2c/versatile_i2c.c

  Log Message:
  -----------
  hw/i2c/versatile_i2c: Add definitions for register addresses

Use self-explicit definitions instead of magic values.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cfcfbae0a1028383d7c084fc4cd3ee958ef78d71
      
https://github.com/qemu/qemu/commit/cfcfbae0a1028383d7c084fc4cd3ee958ef78d71
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/i2c/versatile_i2c.c

  Log Message:
  -----------
  hw/i2c/versatile_i2c: Add SCL/SDA definitions

Use self-explicit definitions instead of magic values.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-4-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f61c3fb56bfad1d76422fa80d18ae5e39a47d61d
      
https://github.com/qemu/qemu/commit/f61c3fb56bfad1d76422fa80d18ae5e39a47d61d
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M MAINTAINERS
    M hw/i2c/versatile_i2c.c
    A include/hw/i2c/arm_sbcon_i2c.h

  Log Message:
  -----------
  hw/i2c: Add header for ARM SBCon two-wire serial bus interface

'ARM SBCon two-wire serial bus interface' is the official
name describing the pair of registers used to bitbanging
I2C in the Versatile boards.

Make the private VersatileI2CState structure as public
ArmSbconI2CState.
Add the TYPE_ARM_SBCON_I2C, alias to our current
TYPE_VERSATILE_I2C model.
Rename the memory region description as 'arm_sbcon_i2c'.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-5-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 440c9f959d20b83c20c589f614cb14fd0dce4546
      
https://github.com/qemu/qemu/commit/440c9f959d20b83c20c589f614cb14fd0dce4546
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/arm/realview.c
    M hw/arm/versatilepb.c
    M hw/arm/vexpress.c

  Log Message:
  -----------
  hw/arm: Use TYPE_VERSATILE_I2C instead of hardcoded string

By using the TYPE_* definitions for devices, we can:
 - quickly find where devices are used with 'git-grep'
 - easily rename a device (one-line change).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-6-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 75ca834136517a48f838537b10318e68abecaed5
      
https://github.com/qemu/qemu/commit/75ca834136517a48f838537b10318e68abecaed5
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Document CMSDK/FPGA APB subsystem sections

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-7-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 90b1b6eff423e1f6dc06b663528ab8d4423fa71f
      
https://github.com/qemu/qemu/commit/90b1b6eff423e1f6dc06b663528ab8d4423fa71f
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Rename CMSDK AHB peripheral region

To differenciate with the CMSDK APB peripheral region,
rename this region 'CMSDK AHB peripheral region'.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-8-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ecbe51aff923b42b453b85471b000d4daa094fe3
      
https://github.com/qemu/qemu/commit/ecbe51aff923b42b453b85471b000d4daa094fe3
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/arm/Kconfig
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Add CMSDK APB watchdog device

We already model the CMSDK APB watchdog device, let's use it!

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-9-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bb8fba9c896dd889e36db8346cd90e17476fca02
      
https://github.com/qemu/qemu/commit/bb8fba9c896dd889e36db8346cd90e17476fca02
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Add CMSDK AHB GPIO peripherals as unimplemented devices

Register the GPIO peripherals as unimplemented to better
follow their accesses, for example booting Zephyr:

  ----------------
  IN: arm_mps2_pinmux_init
  0x00001160:  f64f 0231  movw     r2, #0xf831
  0x00001164:  4b06       ldr      r3, [pc, #0x18]
  0x00001166:  2000       movs     r0, #0
  0x00001168:  619a       str      r2, [r3, #0x18]
  0x0000116a:  f24c 426f  movw     r2, #0xc46f
  0x0000116e:  f503 5380  add.w    r3, r3, #0x1000
  0x00001172:  619a       str      r2, [r3, #0x18]
  0x00001174:  f44f 529e  mov.w    r2, #0x13c0
  0x00001178:  f503 5380  add.w    r3, r3, #0x1000
  0x0000117c:  619a       str      r2, [r3, #0x18]
  0x0000117e:  4770       bx       lr
  cmsdk-ahb-gpio: unimplemented device write (size 4, value 0xf831, offset 0x18)
  cmsdk-ahb-gpio: unimplemented device write (size 4, value 0xc46f, offset 0x18)
  cmsdk-ahb-gpio: unimplemented device write (size 4, value 0x13c0, offset 0x18)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-10-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: adbb23b6a88341fa66a8cfaebedeeadd9a7ac891
      
https://github.com/qemu/qemu/commit/adbb23b6a88341fa66a8cfaebedeeadd9a7ac891
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Map the FPGA I/O block

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-11-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 58f7f3c4526ce90accc87006531e12971a366f67
      
https://github.com/qemu/qemu/commit/58f7f3c4526ce90accc87006531e12971a366f67
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/arm/Kconfig
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Add SPI devices

>From 'Application Note AN385', chapter 3.9, SPI:

  The SMM implements five PL022 SPI modules.

Two pairs of modules share the same OR-gated IRQ.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-12-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ada45de9ea67b814a879a6151361c50122326e76
      
https://github.com/qemu/qemu/commit/ada45de9ea67b814a879a6151361c50122326e76
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/arm/Kconfig
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Add I2C devices

>From 'Application Note AN385', chapter 3.14:

  The SMM implements a simple SBCon interface based on I2C.

There are 4 SBCon interfaces on the FPGA APB subsystem.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-13-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7b465641ed6fd037f577666c0edd5d389ae39696
      
https://github.com/qemu/qemu/commit/7b465641ed6fd037f577666c0edd5d389ae39696
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Add audio I2S interface as unimplemented device

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-14-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2e34818f08d28812e8efa319a4db36668348ac9b
      
https://github.com/qemu/qemu/commit/2e34818f08d28812e8efa319a4db36668348ac9b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Use the ARM SBCon two-wire serial bus interface

>From 'Application Note AN521', chapter 4.7:

  The SMM implements four SBCon serial modules:

  One SBCon module for use by the Color LCD touch interface.
  One SBCon module to configure the audio controller.
  Two general purpose SBCon modules, that connect to the
  Expansion headers J7 and J8, are intended for use with the
  V2C-Shield1 which provide an I2C interface on the headers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-15-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7d20e6815bf5ab678a55673224340b39218be510
      
https://github.com/qemu/qemu/commit/7d20e6815bf5ab678a55673224340b39218be510
  Author: Philippe Mathieu-Daudé <philmd@redhat.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu64.c
    M target/arm/kvm.c
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  target/arm: Check supported KVM features globally (not per vCPU)

Since commit d70c996df23f, when enabling the PMU we get:

  $ qemu-system-aarch64 -cpu host,pmu=on -M virt,accel=kvm,gic-version=3
  Segmentation fault (core dumped)

  Thread 1 "qemu-system-aar" received signal SIGSEGV, Segmentation fault.
  0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at 
accel/kvm/kvm-all.c:2588
  2588        ret = ioctl(s->fd, type, arg);
  (gdb) bt
  #0  0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at 
accel/kvm/kvm-all.c:2588
  #1  0x0000aaaaaae31568 in kvm_check_extension (s=0x0, extension=126) at 
accel/kvm/kvm-all.c:916
  #2  0x0000aaaaaafce254 in kvm_arm_pmu_supported (cpu=0xaaaaac214ab0) at 
target/arm/kvm.c:213
  #3  0x0000aaaaaafc0f94 in arm_set_pmu (obj=0xaaaaac214ab0, value=true, 
errp=0xffffffffe438) at target/arm/cpu.c:1111
  #4  0x0000aaaaab5533ac in property_set_bool (obj=0xaaaaac214ab0, 
v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", opaque=0xaaaaac222730, 
errp=0xffffffffe438) at qom/object.c:2170
  #5  0x0000aaaaab5512f0 in object_property_set (obj=0xaaaaac214ab0, 
v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at 
qom/object.c:1328
  #6  0x0000aaaaab551e10 in object_property_parse (obj=0xaaaaac214ab0, 
string=0xaaaaac11b4c0 "on", name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at 
qom/object.c:1561
  #7  0x0000aaaaab54ee8c in object_apply_global_props (obj=0xaaaaac214ab0, 
props=0xaaaaac018e20, errp=0xaaaaabd6fd88 <error_fatal>) at qom/object.c:407
  #8  0x0000aaaaab1dd5a4 in qdev_prop_set_globals (dev=0xaaaaac214ab0) at 
hw/core/qdev-properties.c:1218
  #9  0x0000aaaaab1d9fac in device_post_init (obj=0xaaaaac214ab0) at 
hw/core/qdev.c:1050
  ...
  #15 0x0000aaaaab54f310 in object_initialize_with_type (obj=0xaaaaac214ab0, 
size=52208, type=0xaaaaabe237f0) at qom/object.c:512
  #16 0x0000aaaaab54fa24 in object_new_with_type (type=0xaaaaabe237f0) at 
qom/object.c:687
  #17 0x0000aaaaab54fa80 in object_new (typename=0xaaaaabe23970 "host-arm-cpu") 
at qom/object.c:702
  #18 0x0000aaaaaaf04a74 in machvirt_init (machine=0xaaaaac0a8550) at 
hw/arm/virt.c:1770
  #19 0x0000aaaaab1e8720 in machine_run_board_init (machine=0xaaaaac0a8550) at 
hw/core/machine.c:1138
  #20 0x0000aaaaaaf95394 in qemu_init (argc=5, argv=0xffffffffea58, 
envp=0xffffffffea88) at softmmu/vl.c:4348
  #21 0x0000aaaaaada3f74 in main (argc=<optimized out>, argv=<optimized out>, 
envp=<optimized out>) at softmmu/main.c:48

This is because in frame #2, cpu->kvm_state is still NULL
(the vCPU is not yet realized).

KVM has a hard requirement of all cores supporting the same
feature set. We only need to check if the accelerator supports
a feature, not each vCPU individually.

Fix by removing the 'CPUState *cpu' argument from the
kvm_arm_<FEATURE>_supported() functions.

Fixes: d70c996df23f ('Use CPUState::kvm_state in kvm_arm_pmu_supported')
Reported-by: Haibo Xu <haibo.xu@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 92a70997ad6dcff865b0071475a878a4fa478da5
      
https://github.com/qemu/qemu/commit/92a70997ad6dcff865b0071475a878a4fa478da5
  Author: Andrew Jones <drjones@redhat.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M tests/qtest/arm-cpu-features.c

  Log Message:
  -----------
  tests/qtest/arm-cpu-features: Add feature setting tests

Some cpu features may be enabled and disabled for all configurations
that support the feature. Let's test that.

A recent regression[*] inspired adding these tests.

[*] '-cpu host,pmu=on' caused a segfault

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200623090622.30365-2-philmd@redhat.com
Message-Id: <20200623082310.17577-1-drjones@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 539533b85fbd269f777bed931de8ccae1dd837e9
      
https://github.com/qemu/qemu/commit/539533b85fbd269f777bed931de8ccae1dd837e9
  Author: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M hw/acpi/generic_event_device.c
    M hw/arm/virt.c

  Log Message:
  -----------
  arm/virt: Add memory hot remove support

This adds support for memory(pc-dimm) hot remove on arm/virt that
uses acpi ged device.

NVDIMM hot removal is not yet supported.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Message-id: 20200622124157.20360-1-shameerali.kolothum.thodi@huawei.com
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d4b78317b7cf8c0c635b70086503813f79ff21ec
      
https://github.com/qemu/qemu/commit/d4b78317b7cf8c0c635b70086503813f79ff21ec
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-23 (Tue, 23 Jun 2020)

  Changed paths:
    M MAINTAINERS
    M hw/acpi/generic_event_device.c
    M hw/arm/Kconfig
    M hw/arm/mps2-tz.c
    M hw/arm/mps2.c
    M hw/arm/realview.c
    M hw/arm/versatilepb.c
    M hw/arm/vexpress.c
    M hw/arm/virt.c
    M hw/i2c/versatile_i2c.c
    M hw/watchdog/cmsdk-apb-watchdog.c
    M hw/watchdog/trace-events
    A include/hw/i2c/arm_sbcon_i2c.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/kvm.c
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h
    M target/arm/neon-dp.decode
    M target/arm/translate-a64.c
    M target/arm/translate-neon.inc.c
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c
    M target/arm/translate.h
    M tests/qtest/arm-cpu-features.c
    M util/oslib-posix.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200623' 
into staging

target-arm queue:
 * util/oslib-posix : qemu_init_exec_dir implementation for Mac
 * target/arm: Last parts of neon decodetree conversion
 * hw/arm/virt: Add 5.0 HW compat props
 * hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
 * mps2: Add CMSDK APB watchdog, FPGAIO block, S2I devices and I2C devices
 * mps2: Add some unimplemented-device stubs for audio and GPIO
 * mps2-tz: Use the ARM SBCon two-wire serial bus interface
 * target/arm: Check supported KVM features globally (not per vCPU)
 * tests/qtest/arm-cpu-features: Add feature setting tests
 * arm/virt: Add memory hot remove support

# gpg: Signature made Tue 23 Jun 2020 12:38:31 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200623: (42 commits)
  arm/virt: Add memory hot remove support
  tests/qtest/arm-cpu-features: Add feature setting tests
  target/arm: Check supported KVM features globally (not per vCPU)
  hw/arm/mps2-tz: Use the ARM SBCon two-wire serial bus interface
  hw/arm/mps2: Add audio I2S interface as unimplemented device
  hw/arm/mps2: Add I2C devices
  hw/arm/mps2: Add SPI devices
  hw/arm/mps2: Map the FPGA I/O block
  hw/arm/mps2: Add CMSDK AHB GPIO peripherals as unimplemented devices
  hw/arm/mps2: Add CMSDK APB watchdog device
  hw/arm/mps2: Rename CMSDK AHB peripheral region
  hw/arm/mps2: Document CMSDK/FPGA APB subsystem sections
  hw/arm: Use TYPE_VERSATILE_I2C instead of hardcoded string
  hw/i2c: Add header for ARM SBCon two-wire serial bus interface
  hw/i2c/versatile_i2c: Add SCL/SDA definitions
  hw/i2c/versatile_i2c: Add definitions for register addresses
  hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
  target/arm: Remove dead code relating to SABA and UABA
  target/arm: Remove unnecessary gen_io_end() calls
  target/arm: Move some functions used only in translate-neon.inc.c to that file
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/d88d5a3806d7...d4b78317b7cf
[Prev in Thread]
Current Thread
[Next in Thread]
[Qemu-commits] [qemu/qemu] c62288: hw/arm/virt: Add 5.0 HW compat props, Peter Maydell <=
Prev by Date: [Qemu-commits] [qemu/qemu] 65b8dc: MAINTAINERS: Cover sh_intc files in the R2D/Shix m...
Next by Date: [Qemu-commits] [qemu/qemu] 8a5fee: docs/specs/tpm: Correct header path name
Previous by thread: [Qemu-commits] [qemu/qemu] 65b8dc: MAINTAINERS: Cover sh_intc files in the R2D/Shix m...
Next by thread: [Qemu-commits] [qemu/qemu] 8a5fee: docs/specs/tpm: Correct header path name
Index(es):
- Date
- Thread