[Qemu-commits] [qemu/qemu] 9593a3: target/arm: Fix missing temp frees in

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[Qemu-commits] [qemu/qemu] 9593a3: target/arm: Fix missing temp frees in

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 9593a3: target/arm: Fix missing temp frees in do_vshll_2sh
Date:	Tue, 16 Jun 2020 06:45:29 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9593a3988c3e788790aa107d778386b09f456a6d
      
https://github.com/qemu/qemu/commit/9593a3988c3e788790aa107d778386b09f456a6d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/translate-neon.inc.c

  Log Message:
  -----------
  target/arm: Fix missing temp frees in do_vshll_2sh

The widenfn() in do_vshll_2sh() does not free the input 32-bit
TCGv, so we need to do this in the calling code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: b28be09570d0827969b62b8f82b0f720a9915427
      
https://github.com/qemu/qemu/commit/b28be09570d0827969b62b8f82b0f720a9915427
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-diff prewidening ops to decodetree

Convert the "pre-widening" insns VADDL, VSUBL, VADDW and VSUBW
in the Neon 3-registers-different-lengths group to decodetree.
These insns work by widening one or both inputs to double their
size, performing an add or subtract at the doubled size and
then storing the double-size result.

As usual, rather than copying the loop of the original decoder
(which needs awkward code to avoid problems when source and
destination registers overlap) we just unroll the two passes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0fa1ab0302badabc3581aefcbb2f189ef52c4985
      
https://github.com/qemu/qemu/commit/0fa1ab0302badabc3581aefcbb2f189ef52c4985
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-diff narrowing ops to decodetree

Convert the narrow-to-high-half insns VADDHN, VSUBHN, VRADDHN,
VRSUBHN in the Neon 3-registers-different-lengths group to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f5b28401200ec95ba89552df3ecdcdc342f6b90b
      
https://github.com/qemu/qemu/commit/f5b28401200ec95ba89552df3ecdcdc342f6b90b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-diff VABAL, VABDL to decodetree

Convert the Neon 3-reg-diff insns VABAL and VABDL to decodetree.
Like almost all the remaining insns in this group, these are
a combination of a two-input operation which returns a double width
result and then a possible accumulation of that double width
result into the destination.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3a1d9eb07b767a7592abca642af80906f9eab0ed
      
https://github.com/qemu/qemu/commit/3a1d9eb07b767a7592abca642af80906f9eab0ed
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-diff long multiplies

Convert the Neon 3-reg-diff insns VMULL, VMLAL and VMLSL; these perform
a 32x32->64 multiply with possible accumulate.

Note that for VMLSL we do the accumulate directly with a subtraction
rather than doing a negate-then-add as the old code did.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9546ca5998d3cbd98a81b2d46a2e92a11b0f78a4
      
https://github.com/qemu/qemu/commit/9546ca5998d3cbd98a81b2d46a2e92a11b0f78a4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-diff saturating doubling multiplies


Convert the Neon 3-reg-diff insns VQDMULL, VQDMLAL and VQDMLSL:
these are all saturating doubling long multiplies with a possible
accumulate step.

These are the last insns in the group which use the pass-over-each
elements loop, so we can delete that code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 18fb58d588898550919392277787979ee7d0d84e
      
https://github.com/qemu/qemu/commit/18fb58d588898550919392277787979ee7d0d84e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-diff polynomial VMULL

Convert the Neon 3-reg-diff insn polynomial VMULL. This is the last
insn in this group to be converted.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 448f0e5f3ecfbd089b934e5e3aa0ccd1f51a6174
      
https://github.com/qemu/qemu/commit/448f0e5f3ecfbd089b934e5e3aa0ccd1f51a6174
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/translate-neon.inc.c

  Log Message:
  -----------
  target/arm: Add 'static' and 'const' annotations to VSHLL function arrays

Mark the arrays of function pointers in trans_VSHLL_S_2sh() and
trans_VSHLL_U_2sh() as both 'static' and 'const'.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a4f67e180def790ff0bbb33fc93bb6e80382f041
      
https://github.com/qemu/qemu/commit/a4f67e180def790ff0bbb33fc93bb6e80382f041
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/translate-neon.inc.c

  Log Message:
  -----------
  target/arm: Add missing TCG temp free in do_2shift_env_64()

In commit 37bfce81b10450071 we accidentally introduced a leak of a TCG
temporary in do_2shift_env_64(); free it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 96fc80f5f186decd1a649f6c04252faceb057ad2
      
https://github.com/qemu/qemu/commit/96fc80f5f186decd1a649f6c04252faceb057ad2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-scalar integer multiplies to decodetree

Convert the VMLA, VMLS and VMUL insns in the Neon "2 registers and a
scalar" group to decodetree.  These are 32x32->32 operations where
one of the inputs is the scalar, followed by a possible accumulate
operation of the 32-bit result.

The refactoring removes some of the oddities of the old decoder:
 * operands to the operation and accumulation were often
   reversed (taking advantage of the fact that most of these ops
   are commutative); the new code follows the pseudocode order
 * the Q bit in the insn was in a local variable 'u'; in the
   new code it is decoded into a->q

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 85ac9aef9a5418de3168df569e21258e853840a2
      
https://github.com/qemu/qemu/commit/85ac9aef9a5418de3168df569e21258e853840a2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-scalar float multiplies to decodetree

Convert the float versions of VMLA, VMLS and VMUL in the Neon
2-reg-scalar group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
As noted in the comment on the WRAP_FP_FN macro, we could have
had a do_2scalar_fp() function, but for 3 insns it seemed
simpler to just do the wrapping to get hold of the fpstatus ptr.
(These are the only fp insns in the group.)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b2fc7be972b94872f6a6dd32d9bda1b88ddbcaad
      
https://github.com/qemu/qemu/commit/b2fc7be972b94872f6a6dd32d9bda1b88ddbcaad
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-scalar VQDMULH, VQRDMULH to decodetree

Convert the VQDMULH and VQRDMULH insns in the 2-reg-scalar group
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: aa318f5b9b4ab3b6744b5305dd8ae9b96676f20e
      
https://github.com/qemu/qemu/commit/aa318f5b9b4ab3b6744b5305dd8ae9b96676f20e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-scalar VQRDMLAH, VQRDMLSH to decodetree

Convert the VQRDMLAH and VQRDMLSH insns in the 2-reg-scalar
group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 77e576a9281825fc170f3b3af83f47e110549b5c
      
https://github.com/qemu/qemu/commit/77e576a9281825fc170f3b3af83f47e110549b5c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 2-reg-scalar long multiplies to decodetree

Convert the Neon 2-reg-scalar long multiplies to decodetree.
These are the last instructions in the group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0aad761fb0aed40c99039eacac470cbd03d07019
      
https://github.com/qemu/qemu/commit/0aad761fb0aed40c99039eacac470cbd03d07019
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VEXT to decodetree

Convert the Neon VEXT insn to decodetree. Rather than keeping the
old implementation which used fixed temporaries cpu_V0 and cpu_V1
and did the extraction with by-hand shift and logic ops, we use
the TCG extract2 insn.

We don't need to special case 0 or 8 immediates any more as the
optimizer is smart enough to throw away the dead code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 54e96c744b70a5d19f14b212a579dd3be8fcaad9
      
https://github.com/qemu/qemu/commit/54e96c744b70a5d19f14b212a579dd3be8fcaad9
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VTBL, VTBX to decodetree

Convert the Neon VTBL, VTBX instructions to decodetree.  The actual
implementation of the insn is copied across to the new trans function
unchanged except for renaming 'tmp5' to 'tmp4'.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9aaa23c2ae18e6fb9a291b81baf91341db76dfa0
      
https://github.com/qemu/qemu/commit/9aaa23c2ae18e6fb9a291b81baf91341db76dfa0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VDUP (scalar) to decodetree

Convert the Neon VDUP (scalar) insn to decodetree.  (Note that we
can't call this just "VDUP" as we used that already in vfp.decode for
the "VDUP (general purpose register" insn.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3d26d7d69066f37b994d3a5eb7601311de2dd659
      
https://github.com/qemu/qemu/commit/3d26d7d69066f37b994d3a5eb7601311de2dd659
  Author: Jean-Christophe Dubois <jcd@tribudubois.net>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M hw/misc/imx6ul_ccm.c

  Log Message:
  -----------
  hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers

Some bits of the CCM registers are non writable.

This was left undone in the initial commit (all bits of registers were
writable).

This patch adds the required code to protect the non writable bits.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 20200608133508.550046-1-jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d7a64d0063d15bf2ee574f18e4f3fe82f57a32ca
      
https://github.com/qemu/qemu/commit/d7a64d0063d15bf2ee574f18e4f3fe82f57a32ca
  Author: Erik Smit <erik.lucas.smit@gmail.com>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M hw/net/ftgmac100.c

  Log Message:
  -----------
  Implement configurable descriptor size in ftgmac100

The hardware supports configurable descriptor sizes, configured in the DBLAC
register.

Most drivers use the default 4 word descriptor, which is currently hardcoded,
but Aspeed SDK configures 8 words to store extra data.

Signed-off-by: Erik Smit <erik.lucas.smit@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[PMM: removed unnecessary parens]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9e6f8d8aab3afe6d704054e3fd850bcba5aa20f7
      
https://github.com/qemu/qemu/commit/9e6f8d8aab3afe6d704054e3fd850bcba5aa20f7
  Author: fangying <fangying1@huawei.com>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu64.c
    M target/arm/kvm.c

  Log Message:
  -----------
  target/arm/cpu: adjust virtual time for all KVM arm cpus

Virtual time adjustment was implemented for virt-5.0 machine type,
but the cpu property was enabled only for host-passthrough and max
cpu model.  Let's add it for any KVM arm cpu which has the generic
timer feature enabled.

Signed-off-by: Ying Fang <fangying1@huawei.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200608121243.2076-1-fangying1@huawei.com
[PMM: minor commit message tweak, removed inaccurate
 suggested-by tag]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8095508a9d8af3d83365becf45ef2a58ba3d488a
      
https://github.com/qemu/qemu/commit/8095508a9d8af3d83365becf45ef2a58ba3d488a
  Author: Jean-Christophe Dubois <jcd@tribudubois.net>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M hw/net/imx_fec.c
    M hw/net/trace-events

  Log Message:
  -----------
  hw/net/imx_fec: Convert debug fprintf() to trace events

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Fixed 32-bit format string using PRIx32/PRIx64]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3b2d81766fd9c957a9fcfe997ff3d692e9981c98
      
https://github.com/qemu/qemu/commit/3b2d81766fd9c957a9fcfe997ff3d692e9981c98
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M hw/sd/sdhci-internal.h
    M hw/sd/sdhci.c
    M include/hw/sd/sdhci.h

  Log Message:
  -----------
  sd: sdhci: Implement basic vendor specific register support

The Linux kernel's IMX code now uses vendor specific commands.
This results in endless warnings when booting the Linux kernel.

sdhci-esdhc-imx 2194000.usdhc: esdhc_wait_for_card_clock_gate_off:
        card clock still not gate off in 100us!.

Implement support for the vendor specific command implemented in IMX hardware
to be able to avoid this warning.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200603145258.195920-2-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 64b397417a26509bcdff44ab94356a35c7901c79
      
https://github.com/qemu/qemu/commit/64b397417a26509bcdff44ab94356a35c7901c79
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M hw/arm/fsl-imx25.c
    M hw/arm/fsl-imx6.c
    M hw/arm/fsl-imx6ul.c
    M hw/arm/fsl-imx7.c

  Log Message:
  -----------
  hw: arm: Set vendor property for IMX SDHCI emulations

Set vendor property to IMX to enable IMX specific functionality
in sdhci code.

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200603145258.195920-3-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cb8278cd997f4776b5a38fce7859bbe3b2d8d139
      
https://github.com/qemu/qemu/commit/cb8278cd997f4776b5a38fce7859bbe3b2d8d139
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M hw/arm/fsl-imx25.c
    M hw/arm/fsl-imx6.c
    M hw/arm/fsl-imx6ul.c
    M hw/arm/fsl-imx7.c
    M hw/misc/imx6ul_ccm.c
    M hw/net/ftgmac100.c
    M hw/net/imx_fec.c
    M hw/net/trace-events
    M hw/sd/sdhci-internal.h
    M hw/sd/sdhci.c
    M include/hw/sd/sdhci.h
    M target/arm/cpu.c
    M target/arm/cpu64.c
    M target/arm/kvm.c
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200616' 
into staging

 * hw: arm: Set vendor property for IMX SDHCI emulations
 * sd: sdhci: Implement basic vendor specific register support
 * hw/net/imx_fec: Convert debug fprintf() to trace events
 * target/arm/cpu: adjust virtual time for all KVM arm cpus
 * Implement configurable descriptor size in ftgmac100
 * hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers
 * target/arm: More Neon decodetree conversion work

# gpg: Signature made Tue 16 Jun 2020 10:56:10 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200616: (23 commits)
  hw: arm: Set vendor property for IMX SDHCI emulations
  sd: sdhci: Implement basic vendor specific register support
  hw/net/imx_fec: Convert debug fprintf() to trace events
  target/arm/cpu: adjust virtual time for all KVM arm cpus
  Implement configurable descriptor size in ftgmac100
  hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers
  target/arm: Convert Neon VDUP (scalar) to decodetree
  target/arm: Convert Neon VTBL, VTBX to decodetree
  target/arm: Convert Neon VEXT to decodetree
  target/arm: Convert Neon 2-reg-scalar long multiplies to decodetree
  target/arm: Convert Neon 2-reg-scalar VQRDMLAH, VQRDMLSH to decodetree
  target/arm: Convert Neon 2-reg-scalar VQDMULH, VQRDMULH to decodetree
  target/arm: Convert Neon 2-reg-scalar float multiplies to decodetree
  target/arm: Convert Neon 2-reg-scalar integer multiplies to decodetree
  target/arm: Add missing TCG temp free in do_2shift_env_64()
  target/arm: Add 'static' and 'const' annotations to VSHLL function arrays
  target/arm: Convert Neon 3-reg-diff polynomial VMULL
  target/arm: Convert Neon 3-reg-diff saturating doubling multiplies
  target/arm: Convert Neon 3-reg-diff long multiplies
  target/arm: Convert Neon 3-reg-diff VABAL, VABDL to decodetree
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#       hw/arm/fsl-imx25.c
#       hw/arm/fsl-imx6.c
#       hw/arm/fsl-imx6ul.c
#       hw/arm/fsl-imx7.c


Compare: https://github.com/qemu/qemu/compare/6675a653d2e5...cb8278cd997f
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