[Qemu-commits] [qemu/qemu] ab553e: target/arm: Make VQDMULL undefined when U=1

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ab553ef74ee52c0889679d0bd0da084aaf938f5c
      
https://github.com/qemu/qemu/commit/ab553ef74ee52c0889679d0bd0da084aaf938f5c
  Author: Fredrik Strupe <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Make VQDMULL undefined when U=1

According to Arm ARM, VQDMULL is only valid when U=0, while having
U=1 is unallocated.

Signed-off-by: Fredrik Strupe <address@hidden>
Fixes: 695272dcb976 ("target-arm: Handle UNDEF cases for Neon 
3-regs-different-widths")
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2e256c04c1852efd6a9b48e61fbcaced4b074c4e
      
https://github.com/qemu/qemu/commit/2e256c04c1852efd6a9b48e61fbcaced4b074c4e
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string

By using the TYPE_* definitions for devices, we can:
 - quickly find where devices are used with 'git-grep'
 - easily rename a device (one-line change).

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bf05340cb655637451162c02dadcd6581a05c02c
      
https://github.com/qemu/qemu/commit/bf05340cb655637451162c02dadcd6581a05c02c
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/cpu-param.h
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Don't use a TLB for ARMMMUIdx_Stage2

We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU
TLB.  However we never actually use the TLB -- all stage 2 lookups
are done by direct calls to get_phys_addr_lpae() followed by a
physical address load via address_space_ld*().

Remove Stage2 from the list of ARM MMU indexes which correspond to
real core MMU indexes, and instead put it in the set of "NOTLB" ARM
MMU indexes.

This allows us to drop NB_MMU_MODES to 11.  It also means we can
safely add support for the ARMv8.3-TTS2UXN extension, which adds
permission bits to the stage 2 descriptors which define execute
permission separatel for EL0 and EL1; supporting that while keeping
Stage2 in a QEMU TLB would require us to use separate TLBs for
"Stage2 for an EL0 access" and "Stage2 for an EL1 access", which is a
lot of extra complication given we aren't even using the QEMU TLB.

In the process of updating the comment on our MMU index use,
fix a couple of other minor errors:
 * NS EL2 EL2&0 was missing from the list in the comment
 * some text hadn't been updated from when we bumped NB_MMU_MODES
   above 8

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 59dff859cd850876df2cfa561c7bcfc4bdda4599
      
https://github.com/qemu/qemu/commit/59dff859cd850876df2cfa561c7bcfc4bdda4599
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Use enum constant in get_phys_addr_lpae() call

The access_type argument to get_phys_addr_lpae() is an MMUAccessType;
use the enum constant MMU_DATA_LOAD rather than a literal 0 when we
call it in S1_ptw_translate().

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: ff7de2fc2c994030bfb83af9ddc9a3cd70ce3e88
      
https://github.com/qemu/qemu/commit/ff7de2fc2c994030bfb83af9ddc9a3cd70ce3e88
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()

For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know
whether the stage 1 access is for EL0 or not, because whether
exec permission is given can depend on whether this is an EL0
or EL1 access. Add a new argument to get_phys_addr_lpae() so
the call sites can pass this information in.

Since get_phys_addr_lpae() doesn't already have a doc comment,
add one so we have a place to put the documentation of the
semantics of the new s1_is_el0 argument.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: ce3125bed935a12e619a8253c19340ecaa899347
      
https://github.com/qemu/qemu/commit/ce3125bed935a12e619a8253c19340ecaa899347
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement ARMv8.2-TTS2UXN

The ARMv8.2-TTS2UXN feature extends the XN field in stage 2
translation table descriptors from just bit [54] to bits [54:53],
allowing stage 2 to control execution permissions separately for EL0
and EL1. Implement the new semantics of the XN field and enable
the feature for our 'max' CPU.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 5a89dd2385a193aa954a7c9bf4e381f2ba6ae359
      
https://github.com/qemu/qemu/commit/5a89dd2385a193aa954a7c9bf4e381f2ba6ae359
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0

In aarch64_max_initfn() we update both 32-bit and 64-bit ID
registers.  The intended pattern is that for 64-bit ID registers we
use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID
registers use FIELD_DP32 and the uint32_t 'u' register.  For
ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of
this 64-bit ID register would end up always zero.  Luckily at the
moment that's what they should be anyway, so this bug has no visible
effects.

Use the right-sized variable.

Fixes: 3bec78447a958d481991
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: e544f80030121040c8932ff1bd4006f390266c0f
      
https://github.com/qemu/qemu/commit/e544f80030121040c8932ff1bd4006f390266c0f
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Use uint64_t for midr field in CPU state struct

MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.
Represent it in QEMU's ARMCPU struct with a uint64_t, not a
uint32_t.

This fixes an error when compiling with -Werror=conversion
because we were manipulating the register value using a
local uint64_t variable:

  target/arm/cpu64.c: In function ‘aarch64_max_initfn’:
  target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long 
unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value 
[-Werror=conversion]
    628 |         cpu->midr = t;
        |                     ^

and future-proofs us against a possible future architecture
change using some of the top 32 bits.

Suggested-by: Laurent Desnogues <address@hidden>
Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5995a02511cd147212353ee377905112359b6fc1
      
https://github.com/qemu/qemu/commit/5995a02511cd147212353ee377905112359b6fc1
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm: versal: Remove inclusion of arm_gicv3_common.h

Remove inclusion of arm_gicv3_common.h, this already gets
included via xlnx-versal.h.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c07c0c37ad45c6cd1cd9ef94988a4790bb78e287
      
https://github.com/qemu/qemu/commit/c07c0c37ad45c6cd1cd9ef94988a4790bb78e287
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm: versal: Move misplaced comment

Move misplaced comment.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0b79d1baeec2044ff3c7f315aff91729d698e24a
      
https://github.com/qemu/qemu/commit/0b79d1baeec2044ff3c7f315aff91729d698e24a
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c

  Log Message:
  -----------
  hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal

Fix typo xlnx-ve -> xlnx-versal.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 88052ffdd1df6cfe8160662fd4a8cc69f7be63bc
      
https://github.com/qemu/qemu/commit/88052ffdd1df6cfe8160662fd4a8cc69f7be63bc
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm: versal: Embed the UARTs into the SoC type

Embed the UARTs into the SoC type.

Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4bd9b59c05bda9c5a8df84ea63292a9471120b02
      
https://github.com/qemu/qemu/commit/4bd9b59c05bda9c5a8df84ea63292a9471120b02
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm: versal: Embed the GEMs into the SoC type

Embed the GEMs into the SoC type.

Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f4e3fa3726244460c1f3b52e72be6e1e9547f445
      
https://github.com/qemu/qemu/commit/f4e3fa3726244460c1f3b52e72be6e1e9547f445
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm: versal: Embed the ADMAs into the SoC type

Embed the ADMAs into the SoC type.

Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ced18d5e500eada554b42f39adc1f97b993bc324
      
https://github.com/qemu/qemu/commit/ced18d5e500eada554b42f39adc1f97b993bc324
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm: versal: Embed the APUs into the SoC type

Embed the APUs into the SoC type.

Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 724c6e12dd77a5e2bacd50fd3e7fb32244b491c1
      
https://github.com/qemu/qemu/commit/724c6e12dd77a5e2bacd50fd3e7fb32244b491c1
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm: versal: Add support for SD

Add support for SD.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: eb1221c52de6a646942a28422a5c56c84364d5b6
      
https://github.com/qemu/qemu/commit/eb1221c52de6a646942a28422a5c56c84364d5b6
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm: versal: Add support for the RTC

hw/arm: versal: Add support for the RTC.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3afec85c2e635d1ee06ef2884f13602db733cd5a
      
https://github.com/qemu/qemu/commit/3afec85c2e635d1ee06ef2884f13602db733cd5a
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c

  Log Message:
  -----------
  hw/arm: versal-virt: Add support for SD

Add support for SD.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2aca5284b14b7f3bedec7c59e7cc68da26944585
      
https://github.com/qemu/qemu/commit/2aca5284b14b7f3bedec7c59e7cc68da26944585
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c

  Log Message:
  -----------
  hw/arm: versal-virt: Add support for the RTC

Add support for the RTC.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0d787cf1f3c88fa29477e054f8523f6d82d91c98
      
https://github.com/qemu/qemu/commit/0d787cf1f3c88fa29477e054f8523f6d82d91c98
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/translate-vfp.inc.c

  Log Message:
  -----------
  target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check

Somewhere along theline we accidentally added a duplicate
"using D16-D31 when they don't exist" check to do_vfm_dp()
(probably an artifact of a patchseries rebase). Remove it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: d1a6d3b594157425232a1ae5ea7f51b7a1c1aa2e
      
https://github.com/qemu/qemu/commit/d1a6d3b594157425232a1ae5ea7f51b7a1c1aa2e
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Don't allow Thumb Neon insns without FEATURE_NEON

We were accidentally permitting decode of Thumb Neon insns even if
the CPU didn't have the FEATURE_NEON bit set, because the feature
check was being done before the call to disas_neon_data_insn() and
disas_neon_ls_insn() in the Arm decoder but was omitted from the
Thumb decoder.  Push the feature bit check down into the called
functions so it is done for both Arm and Thumb encodings.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 625e3dd44a15dfbe9532daa6454df3f86cf04d3e
      
https://github.com/qemu/qemu/commit/625e3dd44a15dfbe9532daa6454df3f86cf04d3e
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/Makefile.objs
    A target/arm/neon-dp.decode
    A target/arm/neon-ls.decode
    A target/arm/neon-shared.decode
    A target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Add stubs for AArch32 Neon decodetree

Add the infrastructure for building and invoking a decodetree decoder
for the AArch32 Neon encodings.  At the moment the new decoder covers
nothing, so we always fall back to the existing hand-written decode.

We follow the same pattern we did for the VFP decodetree conversion
(commit 78e138bc1f672c145ef6ace74617d and following): code that deals
with Neon will be moving gradually out to translate-neon.vfp.inc,
which we #include into translate.c.

In order to share the decode files between A32 and T32, we
split Neon into 3 parts:
 * data-processing
 * load-store
 * 'shared' encodings

The first two groups of instructions have similar but not identical
A32 and T32 encodings, so we need to manually transform the T32
encoding into the A32 one before calling the decoder; the third group
covers the Neon instructions which are identical in A32 and T32.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: afff8de0d4d55b4ce7c36eb9cdfafe477a35dd75
      
https://github.com/qemu/qemu/commit/afff8de0d4d55b4ce7c36eb9cdfafe477a35dd75
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert VCMLA (vector) to decodetree

Convert the VCMLA (vector) insns in the 3same extension group to
decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 94d5eb7b3f72fbbdee55d7908e9cb6de95949f4b
      
https://github.com/qemu/qemu/commit/94d5eb7b3f72fbbdee55d7908e9cb6de95949f4b
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert VCADD (vector) to decodetree

Convert the VCADD (vector) insns to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 32da0e330d3e5218b669079826496751fb52c1ca
      
https://github.com/qemu/qemu/commit/32da0e330d3e5218b669079826496751fb52c1ca
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert V[US]DOT (vector) to decodetree

Convert the V[US]DOT (vector) insns to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 9a107e7b8a3c87ab63ec830d3d60f319fc577ff7
      
https://github.com/qemu/qemu/commit/9a107e7b8a3c87ab63ec830d3d60f319fc577ff7
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert VFM[AS]L (vector) to decodetree

Convert the VFM[AS]L (vector) insns to decodetree.  This is the last
insn in the legacy decoder for the 3same_ext group, so we can
delete the legacy decoder function for the group entirely.

Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false will correctly be directed
to illegal_op by the "(insn & (1 << 28))" check so they won't fall
into disas_coproc_insn() by mistake.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 7e1b5d615361bb0038cda0e08af41e350e42d081
      
https://github.com/qemu/qemu/commit/7e1b5d615361bb0038cda0e08af41e350e42d081
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert VCMLA (scalar) to decodetree

Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 35f5d4d1747558c6af2d914bcd848dcc30c3b531
      
https://github.com/qemu/qemu/commit/35f5d4d1747558c6af2d914bcd848dcc30c3b531
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert V[US]DOT (scalar) to decodetree

Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group
to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: d27e82f7d02f35e5919bd9cbbcb157f3537069a0
      
https://github.com/qemu/qemu/commit/d27e82f7d02f35e5919bd9cbbcb157f3537069a0
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert VFM[AS]L (scalar) to decodetree

Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
to decodetree. These are the last ones in the group so we can remove
all the legacy decode for the group.

Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false will correctly be directed
to illegal_op by the "(insn & (1 << 28))" check so they won't fall
into disas_coproc_insn() by mistake.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: a27b46304352a0eced45e560e96515dbe3cc174f
      
https://github.com/qemu/qemu/commit/a27b46304352a0eced45e560e96515dbe3cc174f
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-ls.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon load/store multiple structures to decodetree

Convert the Neon "load/store multiple structures" insns to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 3698747c48db871d876a398592c5a23d7580ed4a
      
https://github.com/qemu/qemu/commit/3698747c48db871d876a398592c5a23d7580ed4a
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-ls.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 'load single structure to all lanes' to decodetree

Convert the Neon "load single structure to all lanes" insns to
decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 123ce4e3daba26b760b472687e1fb1ad82cf1993
      
https://github.com/qemu/qemu/commit/123ce4e3daba26b760b472687e1fb1ad82cf1993
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-ls.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 'load/store single structure' to decodetree

Convert the Neon "load/store single structure to one lane" insns to
decodetree.

As this is the last set of insns in the neon load/store group,
we can remove the whole disas_neon_ls_insn() function.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: a4e143ac5b9185f670d2f17ee9cc1a430047cb65
      
https://github.com/qemu/qemu/commit/a4e143ac5b9185f670d2f17ee9cc1a430047cb65
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-a64.h
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree

Convert the Neon 3-reg-same VADD and VSUB insns to decodetree.

Note that we don't need the neon_3r_sizes[op] check here because all
size values are OK for VADD and VSUB; we'll add this when we convert
the first insn that has size restrictions.

For this we need one of the GVecGen*Fn typedefs currently in
translate-a64.h; move them all to translate.h as a block so they
are visible to the 32-bit decoder.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 35a548edb6f5043386183b9f6b4139d99d1f130a
      
https://github.com/qemu/qemu/commit/35a548edb6f5043386183b9f6b4139d99d1f130a
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-same logic ops to decodetree

Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
Note that for the logic ops the 'size' field forms part of their
decode and the actual operations are always bitwise.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 36b59310c38d45213bf860affa90618aa5eeca93
      
https://github.com/qemu/qemu/commit/36b59310c38d45213bf860affa90618aa5eeca93
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree

Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 02bd0cdb64b3e79419ba3a8746cb86430883b3ae
      
https://github.com/qemu/qemu/commit/02bd0cdb64b3e79419ba3a8746cb86430883b3ae
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-same comparisons to decodetree

Convert the Neon comparison ops in the 3-reg-same grouping
to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 7a9497f1cf73667a4744d09673b808c20e067915
      
https://github.com/qemu/qemu/commit/7a9497f1cf73667a4744d09673b808c20e067915
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree

Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping
to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 0de34fd48ad4e44bf5caa2330657ebefa93cea7d
      
https://github.com/qemu/qemu/commit/0de34fd48ad4e44bf5caa2330657ebefa93cea7d
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree

Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the
3-reg-same grouping to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 9aefc6cf9b73f66062d2f914a0136756e7a28211
      
https://github.com/qemu/qemu/commit/9aefc6cf9b73f66062d2f914a0136756e7a28211
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Move gen_ function typedefs to translate.h

We're going to want at least some of the NeonGen* typedefs
for the refactored 32-bit Neon decoder, so move them all
to translate.h since it makes more sense to keep them in
one group.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 9af638cc1f665712522608c5d6b8c03d8fa67666
      
https://github.com/qemu/qemu/commit/9af638cc1f665712522608c5d6b8c03d8fa67666
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-04 (Mon, 04 May 2020)

  Changed paths:
    M hw/arm/mps2-tz.c
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h
    M target/arm/Makefile.objs
    M target/arm/cpu-param.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    A target/arm/neon-dp.decode
    A target/arm/neon-ls.decode
    A target/arm/neon-shared.decode
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    A target/arm/translate-neon.inc.c
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200504' 
into staging

target-arm queue:
 * Start of conversion of Neon insns to decodetree
 * versal board: support SD and RTC
 * Implement ARMv8.2-TTS2UXN
 * Make VQDMULL undefined when U=1
 * Some minor code cleanups

# gpg: Signature made Mon 04 May 2020 13:32:08 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200504: (39 commits)
  target/arm: Move gen_ function typedefs to translate.h
  target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree
  target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree
  target/arm: Convert Neon 3-reg-same comparisons to decodetree
  target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
  target/arm: Convert Neon 3-reg-same logic ops to decodetree
  target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
  target/arm: Convert Neon 'load/store single structure' to decodetree
  target/arm: Convert Neon 'load single structure to all lanes' to decodetree
  target/arm: Convert Neon load/store multiple structures to decodetree
  target/arm: Convert VFM[AS]L (scalar) to decodetree
  target/arm: Convert V[US]DOT (scalar) to decodetree
  target/arm: Convert VCMLA (scalar) to decodetree
  target/arm: Convert VFM[AS]L (vector) to decodetree
  target/arm: Convert V[US]DOT (vector) to decodetree
  target/arm: Convert VCADD (vector) to decodetree
  target/arm: Convert VCMLA (vector) to decodetree
  target/arm: Add stubs for AArch32 Neon decodetree
  target/arm: Don't allow Thumb Neon insns without FEATURE_NEON
  target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/2ef486e76d64...9af638cc1f66