[Qemu-commits] [qemu/qemu] 4b7f95: hw/gpio: Add basic Aspeed GPIO model for AST2400 a...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 4b7f956862dc2db4c5c60762abcb3b6179751cc6
      
https://github.com/qemu/qemu/commit/4b7f956862dc2db4c5c60762abcb3b6179751cc6
  Author: Rashmica Gupta <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M hw/gpio/Makefile.objs
    A hw/gpio/aspeed_gpio.c
    A include/hw/gpio/aspeed_gpio.h

  Log Message:
  -----------
  hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500

GPIO pins are arranged in groups of 8 pins labeled A,B,..,Y,Z,AA,AB,AC.
(Note that the ast2400 controller only goes up to group AB).
A set has four groups (except set AC which only has one) and is
referred to by the groups it is composed of (eg ABCD,EFGH,...,YZAAAB).
Each set is accessed and controlled by a bank of 14 registers.

These registers operate on a per pin level where each bit in the register
corresponds to a pin, except for the command source registers. The command
source registers operate on a per group level where bits 24, 16, 8 and 0
correspond to each group in the set.

 eg. registers for set ABCD:
 |D7...D0|C7...C0|B7...B0|A7...A0| <- GPIOs
 |31...24|23...16|15....8|7.....0| <- bit position

Note that there are a couple of groups that only have 4 pins.

There are two ways that this model deviates from the behaviour of the
actual controller:
(1) The only control source driving the GPIO pins in the model is the ARM
model (as there currently aren't models for the LPC or Coprocessor).

(2) None of the registers in the model are reset tolerant (needs
integration with the watchdog).

Signed-off-by: Rashmica Gupta <address@hidden>
Tested-by: Andrew Jeffery <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: fixed missing header files
      made use of HWADDR_PRIx to fix compilation on windows ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fdcc7c0631144933e955b6ddbbd10325abc7f688
      
https://github.com/qemu/qemu/commit/fdcc7c0631144933e955b6ddbbd10325abc7f688
  Author: Rashmica Gupta <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: add a GPIO controller to the SoC

Signed-off-by: Rashmica Gupta <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3a714681507c561f1b1f509061c1e8e8f501eaf3
      
https://github.com/qemu/qemu/commit/3a714681507c561f1b1f509061c1e8e8f501eaf3
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M hw/arm/aspeed_soc.c

  Log Message:
  -----------
  aspeed: Remove unused SoC definitions

There are no QEMU Aspeed machines using the SoCs "ast2400-a0" or
"ast2400".

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 811a5b1d6c2192cb9092040231dab173758bcca7
      
https://github.com/qemu/qemu/commit/811a5b1d6c2192cb9092040231dab173758bcca7
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M hw/ssi/aspeed_smc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: Use consistent typenames

Improve the naming of the different controller models to ease their
generation when initializing the SoC. The rename of the SMC types is
breaking migration compatibility.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c4e1f0b48322a9bc98c37f8413553cb6131daafe
      
https://github.com/qemu/qemu/commit/c4e1f0b48322a9bc98c37f8413553cb6131daafe
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c
    M hw/ssi/aspeed_smc.c
    M include/hw/ssi/aspeed_smc.h

  Log Message:
  -----------
  aspeed/smc: Add support for DMAs

The FMC controller on the Aspeed SoCs support DMA to access the flash
modules. It can operate in a normal mode, to copy to or from the flash
module mapping window, or in a checksum calculation mode, to evaluate
the best clock settings for reads.

The model introduces two custom address spaces for DMAs: one for the
AHB window of the FMC flash devices and one for the DRAM. The latter
is populated using a "dram" link set from the machine with the RAM
container region.

Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0d72c717029f59fa0531fee419734ad7f14b1331
      
https://github.com/qemu/qemu/commit/0d72c717029f59fa0531fee419734ad7f14b1331
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: Add DMA calibration settings

When doing calibration, the SPI clock rate in the CE0 Control Register
and the read delay cycles in the Read Timing Compensation Register are
set using bit[11:4] of the DMA Control Register.

Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Joel Stanley <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5258c2a69ce6cea0b9ab90f1c83223c0daa8d72c
      
https://github.com/qemu/qemu/commit/5258c2a69ce6cea0b9ab90f1c83223c0daa8d72c
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M hw/ssi/aspeed_smc.c
    M include/hw/ssi/aspeed_smc.h

  Log Message:
  -----------
  aspeed/smc: Inject errors in DMA checksum

Emulate read errors in the DMA Checksum Register for high frequencies
and optimistic settings of the Read Timing Compensation Register. This
will help in tuning the SPI timing calibration algorithm. Errors are
only injected when the property "inject_failure" is set to true as
suggested by Philippe.

The values below are those to expect from the first flash device of
the FMC controller of a palmetto-bmc machine.

Cc: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ae275f71338ad4e567c7f2683bf28e66847eabe4
      
https://github.com/qemu/qemu/commit/ae275f71338ad4e567c7f2683bf28e66847eabe4
  Author: Christian Svensson <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: Calculate checksum on normal DMA

This patch adds the missing checksum calculation on normal DMA transfer.
According to the datasheet this is how the SMC should behave.

Verified on AST1250 that the hardware matches the behaviour.

Signed-off-by: Christian Svensson <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9a937f6cc4c18a335e813882d15c83252d611042
      
https://github.com/qemu/qemu/commit/9a937f6cc4c18a335e813882d15c83252d611042
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M hw/misc/aspeed_scu.c
    M include/hw/misc/aspeed_scu.h

  Log Message:
  -----------
  aspeed/scu: Introduce per-SoC SCU types

and use a class AspeedSCUClass to define each SoC characteristics.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a8f07376c9b3e5bce736bdcf6f49dc63fa4a516b
      
https://github.com/qemu/qemu/commit/a8f07376c9b3e5bce736bdcf6f49dc63fa4a516b
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M hw/misc/aspeed_scu.c
    M hw/timer/aspeed_timer.c
    M include/hw/misc/aspeed_scu.h

  Log Message:
  -----------
  aspeed/scu: Introduce a aspeed_scu_get_apb_freq() routine

The APB frequency can be calculated directly when needed from the
HPLL_PARAM and CLK_SEL register values. This removes useless state in
the model.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d2fac5f678559474134bf1f5915a0bb58d946433
      
https://github.com/qemu/qemu/commit/d2fac5f678559474134bf1f5915a0bb58d946433
  Author: Emilio G. Cota <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M accel/tcg/atomic_template.h

  Log Message:
  -----------
  atomic_template: fix indentation in GEN_ATOMIC_HELPER

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 27a296fce9821e3608d537756cffa6e43a46df3b
      
https://github.com/qemu/qemu/commit/27a296fce9821e3608d537756cffa6e43a46df3b
  Author: Peter Maydell <address@hidden>
  Date:   2019-09-13 (Fri, 13 Sep 2019)

  Changed paths:
    M MAINTAINERS
    M Makefile
    M docs/conf.py
    M docs/interop/conf.py
    M docs/interop/index.rst
    A docs/interop/qemu-ga.rst
    M qemu-doc.texi
    R qemu-ga.texi

  Log Message:
  -----------
  qemu-ga: Convert invocation documentation to rST

The qemu-ga documentation is currently in qemu-ga.texi in
Texinfo format, which we present to the user as:
 * a qemu-ga manpage
 * a section of the main qemu-doc HTML documentation

Convert the documentation to rST format, and present it to
the user as:
 * a qemu-ga manpage
 * part of the interop/ Sphinx manual

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Tested-by: Michael Roth <address@hidden>
Message-id: address@hidden


  Commit: dd25f97c66a75d1508f1d4c6478ed2c95bec428f
      
https://github.com/qemu/qemu/commit/dd25f97c66a75d1508f1d4c6478ed2c95bec428f
  Author: Peter Maydell <address@hidden>
  Date:   2019-09-16 (Mon, 16 Sep 2019)

  Changed paths:
    M MAINTAINERS
    M Makefile
    M accel/tcg/atomic_template.h
    M docs/conf.py
    M docs/interop/conf.py
    M docs/interop/index.rst
    A docs/interop/qemu-ga.rst
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c
    M hw/gpio/Makefile.objs
    A hw/gpio/aspeed_gpio.c
    M hw/misc/aspeed_scu.c
    M hw/ssi/aspeed_smc.c
    M hw/timer/aspeed_timer.c
    M include/hw/arm/aspeed_soc.h
    A include/hw/gpio/aspeed_gpio.h
    M include/hw/misc/aspeed_scu.h
    M include/hw/ssi/aspeed_smc.h
    M qemu-doc.texi
    R qemu-ga.texi

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190913' 
into staging

target-arm queue:
 * aspeed: add a GPIO controller to the SoC
 * aspeed: Various refactorings
 * aspeed: Improve DMA controller modelling
 * atomic_template: fix indentation in GEN_ATOMIC_HELPER
 * qemu-ga: Convert invocation documentation to rST

# gpg: Signature made Fri 13 Sep 2019 16:49:05 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190913:
  qemu-ga: Convert invocation documentation to rST
  atomic_template: fix indentation in GEN_ATOMIC_HELPER
  aspeed/scu: Introduce a aspeed_scu_get_apb_freq() routine
  aspeed/scu: Introduce per-SoC SCU types
  aspeed/smc: Calculate checksum on normal DMA
  aspeed/smc: Inject errors in DMA checksum
  aspeed/smc: Add DMA calibration settings
  aspeed/smc: Add support for DMAs
  aspeed: Use consistent typenames
  aspeed: Remove unused SoC definitions
  aspeed: add a GPIO controller to the SoC
  hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/138985c1ef8b...dd25f97c66a7