[Qemu-commits] [qemu/qemu] 80f4d7: tcg: Fix constant folding of INDEX_op_extract2_i32

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 80f4d7c3ae216c191fb403e149bcba88d6aa40bb
      
https://github.com/qemu/qemu/commit/80f4d7c3ae216c191fb403e149bcba88d6aa40bb
  Author: Richard Henderson <address@hidden>
  Date:   2019-07-14 (Sun, 14 Jul 2019)

  Changed paths:
    M tcg/optimize.c

  Log Message:
  -----------
  tcg: Fix constant folding of INDEX_op_extract2_i32

On a 64-bit host, discard any replications of the 32-bit
sign bit when performing the shift and merge.

Fixes: https://bugs.launchpad.net/bugs/1834496
Tested-by: Christophe Lyon <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 1789d4274b851fb8fdf4a947ce5474c63e813d0d
      
https://github.com/qemu/qemu/commit/1789d4274b851fb8fdf4a947ce5474c63e813d0d
  Author: Richard Henderson <address@hidden>
  Date:   2019-07-14 (Sun, 14 Jul 2019)

  Changed paths:
    M tcg/aarch64/tcg-target.inc.c

  Log Message:
  -----------
  tcg/aarch64: Fix output of extract2 opcodes

This patch fixes two problems:
(1) The inputs to the EXTR insn were reversed,
(2) The input constraints use rZ, which means that we need to use
    the REG0 macro in order to supply XZR for a constant 0 input.

Fixes: 464c2969d5d
Reported-by: Peter Maydell <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 359896dfa4e9707e1acea99129d324250fccab04
      
https://github.com/qemu/qemu/commit/359896dfa4e9707e1acea99129d324250fccab04
  Author: Richard Henderson <address@hidden>
  Date:   2019-07-14 (Sun, 14 Jul 2019)

  Changed paths:
    M include/qemu/atomic.h

  Log Message:
  -----------
  include/qemu/atomic.h: Add signal_barrier

We have some potential race conditions vs our user-exec signal
handler that will be solved with this barrier.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 08b97f7ff299df35c61bc74b8e53dbe23d59470b
      
https://github.com/qemu/qemu/commit/08b97f7ff299df35c61bc74b8e53dbe23d59470b
  Author: Richard Henderson <address@hidden>
  Date:   2019-07-14 (Sun, 14 Jul 2019)

  Changed paths:
    M accel/tcg/user-exec.c
    M include/exec/cpu_ldst.h
    M include/exec/cpu_ldst_useronly_template.h
    M target/arm/helper-a64.c
    M target/arm/sve_helper.c

  Log Message:
  -----------
  tcg: Introduce set/clear_helper_retaddr

At present we have a potential error in that helper_retaddr contains
data for handle_cpu_signal, but we have not ensured that those stores
will be scheduled properly before the operation that may fault.

It might be that these races are not in practice observable, due to
our use of -fno-strict-aliasing, but better safe than sorry.

Adjust all of the setters of helper_retaddr.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 6ad8307bdd93834568b5969cb7e704de15f01a8b
      
https://github.com/qemu/qemu/commit/6ad8307bdd93834568b5969cb7e704de15f01a8b
  Author: Richard Henderson <address@hidden>
  Date:   2019-07-14 (Sun, 14 Jul 2019)

  Changed paths:
    M include/exec/cpu_ldst_useronly_template.h

  Log Message:
  -----------
  tcg: Remove cpu_ld*_code_ra

These functions are not used, and are not usable in the
context of code generation, because we never have a helper
return address to pass in to them.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 2fbb2353ce8d098e172cd25024fc221c1c8e3591
      
https://github.com/qemu/qemu/commit/2fbb2353ce8d098e172cd25024fc221c1c8e3591
  Author: Richard Henderson <address@hidden>
  Date:   2019-07-14 (Sun, 14 Jul 2019)

  Changed paths:
    M include/exec/cpu_ldst_useronly_template.h

  Log Message:
  -----------
  tcg: Remove duplicate #if !defined(CODE_ACCESS)

This code block is already surrounded by #ifndef CODE_ACCESS.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 52ba13f042714c4086416973fb88e2465e0888a1
      
https://github.com/qemu/qemu/commit/52ba13f042714c4086416973fb88e2465e0888a1
  Author: Richard Henderson <address@hidden>
  Date:   2019-07-14 (Sun, 14 Jul 2019)

  Changed paths:
    M accel/tcg/user-exec.c
    M include/exec/cpu_ldst_useronly_template.h

  Log Message:
  -----------
  tcg: Release mmap_lock on translation fault

Turn helper_retaddr into a multi-state flag that may now also
indicate when we're performing a read on behalf of the translator.
In this case, release the mmap_lock before the longjmp back to
the main cpu loop, and thereby avoid a failing assert therein.

Fixes: https://bugs.launchpad.net/qemu/+bug/1832353
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 298ad7b5a4519d2ae547df46103b2f8d49ca6f95
      
https://github.com/qemu/qemu/commit/298ad7b5a4519d2ae547df46103b2f8d49ca6f95
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-15 (Mon, 15 Jul 2019)

  Changed paths:
    M accel/tcg/user-exec.c
    M include/exec/cpu_ldst.h
    M include/exec/cpu_ldst_useronly_template.h
    M include/qemu/atomic.h
    M target/arm/helper-a64.c
    M target/arm/sve_helper.c
    M tcg/aarch64/tcg-target.inc.c
    M tcg/optimize.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190714' into staging

Fixes for 3 tcg bugs

# gpg: Signature made Sun 14 Jul 2019 12:11:01 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Richard Henderson <address@hidden>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20190714:
  tcg: Release mmap_lock on translation fault
  tcg: Remove duplicate #if !defined(CODE_ACCESS)
  tcg: Remove cpu_ld*_code_ra
  tcg: Introduce set/clear_helper_retaddr
  include/qemu/atomic.h: Add signal_barrier
  tcg/aarch64: Fix output of extract2 opcodes
  tcg: Fix constant folding of INDEX_op_extract2_i32

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/46cd24e7ed38...298ad7b5a451