[Qemu-commits] [qemu/qemu] 9dd5cc: target/arm: Move debug routines to debug_helper.c

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9dd5cca42448770a940fa2145f1ff18cdc7b01a9
      
https://github.com/qemu/qemu/commit/9dd5cca42448770a940fa2145f1ff18cdc7b01a9
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-04 (Thu, 04 Jul 2019)

  Changed paths:
    M target/arm/Makefile.objs
    M target/arm/cpu.c
    A target/arm/debug_helper.c
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Move debug routines to debug_helper.c

These routines are TCG specific.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 91f78c58da9ba78c8ed00f5d822b701765be8499
      
https://github.com/qemu/qemu/commit/91f78c58da9ba78c8ed00f5d822b701765be8499
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-04 (Thu, 04 Jul 2019)

  Changed paths:
    M target/arm/Makefile.objs
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Restrict semi-hosting to TCG

Per Peter Maydell:

  Semihosting hooks either SVC or HLT instructions, and inside KVM
  both of those go to EL1, ie to the guest, and can't be trapped to
  KVM.

Let check_for_semihosting() return False when not running on TCG.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7aab5a8c8bb525ea390b4ebc17ab82c0835cfdb6
      
https://github.com/qemu/qemu/commit/7aab5a8c8bb525ea390b4ebc17ab82c0835cfdb6
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-04 (Thu, 04 Jul 2019)

  Changed paths:
    M target/arm/Makefile.objs
    M target/arm/helper.c
    A target/arm/m_helper.c

  Log Message:
  -----------
  target/arm/helper: Move M profile routines to m_helper.c

In preparation for supporting TCG disablement on ARM, we move most
of TCG related v7m/v8m helpers and APIs into their own file.

Note: It is easier to review this commit using the 'histogram'
      diff algorithm:

    $ git diff --diff-algorithm=histogram ...
  or
    $ git diff --histogram ...

Suggested-by: Samuel Ortiz <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: updated qapi #include to match recent changes there]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 077d7449100d824a4e9230e349099399bde3b20f
      
https://github.com/qemu/qemu/commit/077d7449100d824a4e9230e349099399bde3b20f
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-04 (Thu, 04 Jul 2019)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  arm v8M: Forcibly clear negative-priority exceptions on deactivate

To prevent execution priority remaining negative if the guest
returns from an NMI or HardFault with a corrupted IPSR, the
v8M interrupt deactivation process forces the HardFault and NMI
to inactive based on the current raw execution priority,
even if the interrupt the guest is trying to deactivate
is something else. In the pseudocode this is done in the
Deactivate() function.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: be32116e32c3fd51c0d91fd658d534424434e659
      
https://github.com/qemu/qemu/commit/be32116e32c3fd51c0d91fd658d534424434e659
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-04 (Thu, 04 Jul 2019)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  target/arm: v8M: Check state of exception being returned from

In v8M, an attempt to return from an exception which is not
active is an illegal exception return. For this purpose,
exceptions which can configurably target either Secure or
NonSecure are not considered to be active if they are
configured for the opposite security state for the one
we're trying to return from (eg attempt to return from
an NS NMI but NMI targets Secure). In the pseudocode this
is handled by IsActiveForState().

Detect this case rather than counting an active exception
possibly of the wrong security state as being sufficient.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 2884fbb60412049ec92389039ae716b32057382e
      
https://github.com/qemu/qemu/commit/2884fbb60412049ec92389039ae716b32057382e
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-04 (Thu, 04 Jul 2019)

  Changed paths:
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: Use _ra versions of cpu_stl_data() in v7M helpers

In the various helper functions for v7M/v8M instructions, use
the _ra versions of cpu_stl_data() and friends. Otherwise we
may get wrong behaviour or an assert() due to not being able
to locate the TB if there is an exception on the memory access
or if it performs an IO operation when in icount mode.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 9bed521ec894d30c58088e2fa5da43f3814a54d8
      
https://github.com/qemu/qemu/commit/9bed521ec894d30c58088e2fa5da43f3814a54d8
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-04 (Thu, 04 Jul 2019)

  Changed paths:
    M hw/timer/armv7m_systick.c

  Log Message:
  -----------
  hw/timer/armv7m_systick: Forbid non-privileged accesses

Like most of the v7M memory mapped system registers, the systick
registers are accessible to privileged code only and user accesses
must generate a BusFault. We implement that for registers in
the NVIC proper already, but missed it for systick since we
implement it as a separate device. Correct the omission.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 5529de1e5512c05276825fa8b922147663fd6eac
      
https://github.com/qemu/qemu/commit/5529de1e5512c05276825fa8b922147663fd6eac
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-04 (Thu, 04 Jul 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Execute Thumb instructions when their condbits are 0xf

Thumb instructions in an IT block are set up to be conditionally
executed depending on a set of condition bits encoded into the IT
bits of the CPSR/XPSR.  The architecture specifies that if the
condition bits are 0b1111 this means "always execute" (like 0b1110),
not "never execute"; we were treating it as "never execute".  (See
the ConditionHolds() pseudocode in both the A-profile and M-profile
Arm ARM.)

This is a bit of an obscure corner case, because the only legal
way to get to an 0b1111 set of condbits is to do an exception
return which sets the XPSR/CPSR up that way. An IT instruction
which encodes a condition sequence that would include an 0b1111 is
UNPREDICTABLE, and for v8A the CONSTRAINED UNPREDICTABLE choices
for such an IT insn are to NOP, UNDEF, or treat 0b1111 like 0b1110.
Add a comment noting that we take the latter option.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 89a11ff756410aecb87d2c774df6e45dbf4105c1
      
https://github.com/qemu/qemu/commit/89a11ff756410aecb87d2c774df6e45dbf4105c1
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-04 (Thu, 04 Jul 2019)

  Changed paths:
    M target/arm/translate-vfp.inc.c

  Log Message:
  -----------
  target/arm: Correct VMOV_imm_dp handling of short vectors

Coverity points out (CID 1402195) that the loop in trans_VMOV_imm_dp()
that iterates over the destination registers in a short-vector VMOV
accidentally throws away the returned updated register number
from vfp_advance_dreg(). Add the missing assignment. (We got this
correct in trans_VMOV_imm_sp().)

Fixes: 18cf951af9a27ae573a
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 57dfc2c4d51e770ed3f617e5d1456d1e2bacf3f0
      
https://github.com/qemu/qemu/commit/57dfc2c4d51e770ed3f617e5d1456d1e2bacf3f0
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-04 (Thu, 04 Jul 2019)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M hw/timer/armv7m_systick.c
    M target/arm/Makefile.objs
    M target/arm/cpu.c
    M target/arm/cpu.h
    A target/arm/debug_helper.c
    M target/arm/helper.c
    A target/arm/m_helper.c
    M target/arm/op_helper.c
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20190704-1' into staging

target-arm queue:
 * more code-movement to separate TCG-only functions into their own files
 * Correct VMOV_imm_dp handling of short vectors
 * Execute Thumb instructions when their condbits are 0xf
 * armv7m_systick: Forbid non-privileged accesses
 * Use _ra versions of cpu_stl_data() in v7M helpers
 * v8M: Check state of exception being returned from
 * v8M: Forcibly clear negative-priority exceptions on deactivate

# gpg: Signature made Thu 04 Jul 2019 17:31:22 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190704-1:
  target/arm: Correct VMOV_imm_dp handling of short vectors
  target/arm: Execute Thumb instructions when their condbits are 0xf
  hw/timer/armv7m_systick: Forbid non-privileged accesses
  target/arm: Use _ra versions of cpu_stl_data() in v7M helpers
  target/arm: v8M: Check state of exception being returned from
  arm v8M: Forcibly clear negative-priority exceptions on deactivate
  target/arm/helper: Move M profile routines to m_helper.c
  target/arm: Restrict semi-hosting to TCG
  target/arm: Move debug routines to debug_helper.c

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c3e1d838cfa5...57dfc2c4d51e