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[Qemu-commits] [qemu/qemu] c63704: hw/arm/smmuv3: Remove SMMUNotifierNod
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] c63704: hw/arm/smmuv3: Remove SMMUNotifierNode |
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Date: |
Mon, 29 Apr 2019 11:10:47 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: c637044120705004b792ecf29e6b4be41e20c4c8
https://github.com/qemu/qemu/commit/c637044120705004b792ecf29e6b4be41e20c4c8
Author: Eric Auger <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmuv3.c
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmuv3: Remove SMMUNotifierNode
The SMMUNotifierNode struct is not necessary and brings extra
complexity so let's remove it. We now directly track the SMMUDevices
which have registered IOMMU MR notifiers.
This is inspired from the same transformation on intel-iommu
done in commit b4a4ba0d68f50f218ee3957b6638dbee32a5eeef
("intel-iommu: remove IntelIOMMUNotifierNode")
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: aa64cfaeb4ad0e67ccb54fa20511d7a36db9d833
https://github.com/qemu/qemu/commit/aa64cfaeb4ad0e67ccb54fa20511d7a36db9d833
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/ssi/xilinx_spips.c
Log Message:
-----------
hw/ssi/xilinx_spips: Avoid variable length array
In the stripe8() function we use a variable length array; however
we know that the maximum length required is MAX_NUM_BUSSES. Use
a fixed-length array and an assert instead.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Stefano Garzarella <address@hidden>
Message-id: address@hidden
Commit: 79d77bcd366190a81d092177e4f84d34b7a56fc2
https://github.com/qemu/qemu/commit/79d77bcd366190a81d092177e4f84d34b7a56fc2
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M configure
Log Message:
-----------
configure: Remove --source-path option
Normally configure identifies the source path by looking
at the location where the configure script itself exists.
We also provide a --source-path option which lets the user
manually override this.
There isn't really an obvious use case for the --source-path
option, and in commit 927128222b0a91f56c13a in 2017 we
accidentally added some logic that looks at $source_path
before the command line option that overrides it has been
processed.
The fact that nobody complained suggests that there isn't
any use of this option and we aren't testing it either;
remove it. This allows us to move the "make $source_path
absolute" logic up so that there is no window in the script
where $source_path is set but not yet absolute.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Daniel P. Berrangé <address@hidden>
Message-id: address@hidden
Commit: 5bcf8ed9401e62c73158ba110864ee1375558bf7
https://github.com/qemu/qemu/commit/5bcf8ed9401e62c73158ba110864ee1375558bf7
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Make sure M-profile FPSCR RES0 bits are not settable
Enforce that for M-profile various FPSCR bits which are RES0 there
but have defined meanings on A-profile are never settable. This
ensures that M-profile code can't enable the A-profile behaviour
(notably vector length/stride handling) by accident.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 84d2e3e2ae76fdb0c8f3063fa8c46c8ce14ab201
https://github.com/qemu/qemu/commit/84d2e3e2ae76fdb0c8f3063fa8c46c8ce14ab201
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers
For M-profile the MVFR* ID registers are memory mapped, in the
range we implement via the NVIC. Allow them to be read.
(If the CPU has no FPU, these registers are defined to be RAZ.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: d33abe82c7c9847284a23e575e1078cccab540b5
https://github.com/qemu/qemu/commit/d33abe82c7c9847284a23e575e1078cccab540b5
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/machine.c
Log Message:
-----------
target/arm: Implement dummy versions of M-profile FP-related registers
The M-profile floating point support has three associated config
registers: FPCAR, FPCCR and FPDSCR. It also makes the registers
CPACR and NSACR have behaviour other than reads-as-zero.
Add support for all of these as simple reads-as-written registers.
We will hook up actual functionality later.
The main complexity here is handling the FPCCR register, which
has a mix of banked and unbanked bits.
Note that we don't share storage with the A-profile
cpu->cp15.nsacr and cpu->cp15.cpacr_el1, though the behaviour
is quite similar, for two reasons:
* the M profile CPACR is banked between security states
* it preserves the invariant that M profile uses no state
inside the cp15 substruct
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: ef9aae2522c22c05df17dd898099dd5c3f20d688
https://github.com/qemu/qemu/commit/ef9aae2522c22c05df17dd898099dd5c3f20d688
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Disable most VFP sysregs for M-profile
The only "system register" that M-profile floating point exposes
via the VMRS/VMRS instructions is FPSCR, and it does not have
the odd special case for rd==15. Add a check to ensure we only
expose FPSCR.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: d87513c0abcbcd856f8e1dee2f2d18903b2c3ea2
https://github.com/qemu/qemu/commit/d87513c0abcbcd856f8e1dee2f2d18903b2c3ea2
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/helper.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Honour M-profile FP enable bits
Like AArch64, M-profile floating point has no FPEXC enable
bit to gate floating point; so always set the VFPEN TB flag.
M-profile also has CPACR and NSACR similar to A-profile;
they behave slightly differently:
* the CPACR is banked between Secure and Non-Secure
* if the NSACR forces a trap then this is taken to
the Secure state, not the Non-Secure state
Honour the CPACR and NSACR settings. The NSACR handling
requires us to borrow the exception.target_el field
(usually meaningless for M profile) to distinguish the
NOCP UsageFault taken to Secure state from the more
usual fault taken to the current security state.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 8859ba3c9625e7ceb5599f457a344bcd7c5e112b
https://github.com/qemu/qemu/commit/8859ba3c9625e7ceb5599f457a344bcd7c5e112b
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Decode FP instructions for M profile
Correct the decode of the M-profile "coprocessor and
floating-point instructions" space:
* op0 == 0b11 is always unallocated
* if the CPU has an FPU then all insns with op1 == 0b101
are floating point and go to disas_vfp_insn()
For the moment we leave VLLDM and VLSTM as NOPs; in
a later commit we will fill in the proper implementation
for the case where an FPU is present.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 1702071302934af77a072b7ee7c5eadc45b37573
https://github.com/qemu/qemu/commit/1702071302934af77a072b7ee7c5eadc45b37573
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present
If the floating point extension is present, then the SG instruction
must clear the CONTROL_S.SFPA bit. Implement this.
(On a no-FPU system the bit will always be zero, so we don't need
to make the clearing of the bit conditional on ARM_FEATURE_VFP.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 2e1c5bcd32014c9ede1b604ae6c2c653de17fc53
https://github.com/qemu/qemu/commit/2e1c5bcd32014c9ede1b604ae6c2c653de17fc53
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL
The M-profile CONTROL register has two bits -- SFPA and FPCA --
which relate to floating-point support, and should be RES0 otherwise.
Handle them correctly in the MSR/MRS register access code.
Neither is banked between security states, so they are stored
in v7m.control[M_REG_S] regardless of current security state.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 3432c79a4e7345818d2defcf9e61a1bcb2907f9f
https://github.com/qemu/qemu/commit/3432c79a4e7345818d2defcf9e61a1bcb2907f9f
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm/helper: don't return early for STKOF faults during stacking
Currently the code in v7m_push_stack() which detects a violation
of the v8M stack limit simply returns early if it does so. This
is OK for the current integer-only code, but won't work for the
floating point handling we're about to add. We need to continue
executing the rest of the function so that we check for other
exceptions like not having permission to use the FPU and so
that we correctly set the FPCCR state if we are doing lazy
stacking. Refactor to avoid the early return.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 0ed377a8013f40653a83f6ad2c9693897522d7dc
https://github.com/qemu/qemu/commit/0ed377a8013f40653a83f6ad2c9693897522d7dc
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle floating point registers in exception entry
Handle floating point registers in exception entry.
This corresponds to the FP-specific parts of the pseudocode
functions ActivateException() and PushStack().
We defer the code corresponding to UpdateFPCCR() to a later patch.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: b593c2b81287040ab6f452afec6281e2f7ee487b
https://github.com/qemu/qemu/commit/b593c2b81287040ab6f452afec6281e2f7ee487b
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement v7m_update_fpccr()
Implement the code which updates the FPCCR register on an
exception entry where we are going to use lazy FP stacking.
We have to defer to the NVIC to determine whether the
various exceptions are currently ready or not.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 3cd6726f0ba7cc77342ee721bd86094e13b2a42a
https://github.com/qemu/qemu/commit/3cd6726f0ba7cc77342ee721bd86094e13b2a42a
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Clear CONTROL.SFPA in BXNS and BLXNS
For v8M floating point support, transitions from Secure
to Non-secure state via BLNS and BLXNS must clear the
CONTROL.SFPA bit. (This corresponds to the pseudocode
BranchToNS() function.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 60fba59a2f9a092a44b688df5d058cdd6dd9c276
https://github.com/qemu/qemu/commit/60fba59a2f9a092a44b688df5d058cdd6dd9c276
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Clean excReturn bits when tail chaining
The TailChain() pseudocode specifies that a tail chaining
exception should sanitize the excReturn all-ones bits and
(if there is no FPU) the excReturn FType bits; we weren't
doing this.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 0dc51d66fcfcc4c72011cdafb401fd876ca216e7
https://github.com/qemu/qemu/commit/0dc51d66fcfcc4c72011cdafb401fd876ca216e7
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Allow for floating point in callee stack integrity check
The magic value pushed onto the callee stack as an integrity
check is different if floating point is present.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 6808c4d2d2826920087533f517472c09edc7b0d2
https://github.com/qemu/qemu/commit/6808c4d2d2826920087533f517472c09edc7b0d2
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle floating point registers in exception return
Handle floating point registers in exception return.
This corresponds to pseudocode functions ValidateExceptionReturn(),
ExceptionReturn(), PopStack() and ConsumeExcStackFrame().
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 7fbb535f7aeb22896fedfcf18a1eeff48165f1d7
https://github.com/qemu/qemu/commit/7fbb535f7aeb22896fedfcf18a1eeff48165f1d7
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Move NS TBFLAG from bit 19 to bit 6
Move the NS TBFLAG down from bit 19 to bit 6, which has not
been used since commit c1e3781090b9d36c60 in 2015, when we
started passing the entire MMU index in the TB flags rather
than just a 'privilege level' bit.
This rearrangement is not strictly necessary, but means that
we can put M-profile-only bits next to each other rather
than scattered across the flag word.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: ea7ac69d124c94c6e5579145e727adec9ccbefef
https://github.com/qemu/qemu/commit/ea7ac69d124c94c6e5579145e727adec9ccbefef
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags
We are close to running out of TB flags for AArch32; we could
start using the cs_base word, but before we do that we can
economise on our usage by sharing the same bits for the VFP
VECSTRIDE field and the XScale XSCALE_CPAR field. This
works because no XScale CPU ever had VFP.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 6d60c67a1a03be32c3342aff6604cdc5095088d1
https://github.com/qemu/qemu/commit/6d60c67a1a03be32c3342aff6604cdc5095088d1
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Set FPCCR.S when executing M-profile floating point insns
The M-profile FPCCR.S bit indicates the security status of
the floating point context. In the pseudocode ExecuteFPCheck()
function it is unconditionally set to match the current
security state whenever a floating point instruction is
executed.
Implement this by adding a new TB flag which tracks whether
FPCCR.S is different from the current security state, so
that we only need to emit the code to update it in the
less-common case when it is not already set correctly.
Note that we will add the handling for the other work done
by ExecuteFPCheck() in later commits.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 6000531e19964756673a5f4b694a649ef883605a
https://github.com/qemu/qemu/commit/6000531e19964756673a5f4b694a649ef883605a
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Activate M-profile floating point context when FPCCR.ASPEN is set
The M-profile FPCCR.ASPEN bit indicates that automatic floating-point
context preservation is enabled. Before executing any floating-point
instruction, if FPCCR.ASPEN is set and the CONTROL FPCA/SFPA bits
indicate that there is no active floating point context then we
must create a new context (by initializing FPSCR and setting
FPCA/SFPA to indicate that the context is now active). In the
pseudocode this is handled by ExecuteFPCheck().
Implement this with a new TB flag which tracks whether we
need to create a new FP context.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: fa6252a988dbe440cd6087bf93cbe0887f0c401b
https://github.com/qemu/qemu/commit/fa6252a988dbe440cd6087bf93cbe0887f0c401b
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: New helper function arm_v7m_mmu_idx_all()
Add a new helper function which returns the MMU index to use
for v7M, where the caller specifies all of the security
state, privilege level and whether the execution priority
is negative, and reimplement the existing
arm_v7m_mmu_idx_for_secstate_and_priv() in terms of it.
We are going to need this for the lazy-FP-stacking code.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: a99ba8ab1601904e0fa20325192fc850362ce80e
https://github.com/qemu/qemu/commit/a99ba8ab1601904e0fa20325192fc850362ce80e
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
Log Message:
-----------
target/arm: New function armv7m_nvic_set_pending_lazyfp()
In the v7M architecture, if an exception is generated in the process
of doing the lazy stacking of FP registers, the handling of
possible escalation to HardFault is treated differently to the normal
approach: it works based on the saved information about exception
readiness that was stored in the FPCCR when the stack frame was
created. Provide a new function armv7m_nvic_set_pending_lazyfp()
which pends exceptions during lazy stacking, and implements
this logic.
This corresponds to the pseudocode TakePreserveFPException().
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: a356dacf647506bccdf8ecd23574246a8bf615ac
https://github.com/qemu/qemu/commit/a356dacf647506bccdf8ecd23574246a8bf615ac
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Add lazy-FP-stacking support to v7m_stack_write()
Pushing registers to the stack for v7M needs to handle three cases:
* the "normal" case where we pend exceptions
* an "ignore faults" case where we set FSR bits but
do not pend exceptions (this is used when we are
handling some kinds of derived exception on exception entry)
* a "lazy FP stacking" case, where different FSR bits
are set and the exception is pended differently
Implement this by changing the existing flag argument that
tells us whether to ignore faults or not into an enum that
specifies which of the 3 modes we should handle.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: e33cf0f8d8c9998a7616684f9d6aa0d181b88803
https://github.com/qemu/qemu/commit/e33cf0f8d8c9998a7616684f9d6aa0d181b88803
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement M-profile lazy FP state preservation
The M-profile architecture floating point system supports
lazy FP state preservation, where FP registers are not
pushed to the stack when an exception occurs but are instead
only saved if and when the first FP instruction in the exception
handler is executed. Implement this in QEMU, corresponding
to the check of LSPACT in the pseudocode ExecuteFPCheck().
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 019076b036da4444494de38388218040d9d3a26c
https://github.com/qemu/qemu/commit/019076b036da4444494de38388218040d9d3a26c
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement VLSTM for v7M CPUs with an FPU
Implement the VLSTM instruction for v7M for the FPU present case.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 956fe143b4f254356496a0a1c479fa632376dfec
https://github.com/qemu/qemu/commit/956fe143b4f254356496a0a1c479fa632376dfec
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/helper.c
M target/arm/helper.h
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement VLLDM for v7M CPUs with an FPU
Implement the VLLDM instruction for v7M for the FPU present cas.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 14fd0c31e26b88a2189b3f459b864d5e1faf302a
https://github.com/qemu/qemu/commit/14fd0c31e26b88a2189b3f459b864d5e1faf302a
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Enable FPU for Cortex-M4 and Cortex-M33
Enable the FPU by default for the Cortex-M4 and Cortex-M33.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 597e76f2fa526c65eb761d2cca4debdc21513305
https://github.com/qemu/qemu/commit/597e76f2fa526c65eb761d2cca4debdc21513305
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/dma/Makefile.objs
Log Message:
-----------
hw/dma: Compile the bcm2835_dma device as common object
This device is used by both ARM (BCM2836, for raspi2) and AArch64
(BCM2837, for raspi3) targets, and is not CPU-specific.
Move it to common object, so we build it once for all targets.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 044475f394fc05c964372f30c64ffe025101c73b
https://github.com/qemu/qemu/commit/044475f394fc05c964372f30c64ffe025101c73b
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Use TYPE_TMP105/TYPE_PCA9552 instead of hardcoded string
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5f299c5592267f132ace1a7b883f96f2512c9743
https://github.com/qemu/qemu/commit/5f299c5592267f132ace1a7b883f96f2512c9743
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/arm/nseries.c
Log Message:
-----------
hw/arm/nseries: Use TYPE_TMP105 instead of hardcoded string
Suggested-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: fae06a33f0f107619f3b55da41e548eaf317de4d
https://github.com/qemu/qemu/commit/fae06a33f0f107619f3b55da41e548eaf317de4d
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/display/tc6393xb.c
M include/hw/devices.h
Log Message:
-----------
hw/display/tc6393xb: Remove unused functions
No code used the tc6393xb_gpio_in_get() and tc6393xb_gpio_out_set()
functions since their introduction in commit 88d2c950b002. Time to
remove them.
Suggested-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: ee2ccc57e96f3f4a592d04d9f994226d470057bf
https://github.com/qemu/qemu/commit/ee2ccc57e96f3f4a592d04d9f994226d470057bf
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M MAINTAINERS
M hw/arm/tosa.c
M hw/display/tc6393xb.c
M include/hw/devices.h
A include/hw/display/tc6393xb.h
Log Message:
-----------
hw/devices: Move TC6393XB declarations into a new header
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8a08cc71d29b7ff43d91d37303f40aa89f65c617
https://github.com/qemu/qemu/commit/8a08cc71d29b7ff43d91d37303f40aa89f65c617
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M MAINTAINERS
M hw/arm/nseries.c
M hw/display/blizzard.c
M include/hw/devices.h
A include/hw/display/blizzard.h
Log Message:
-----------
hw/devices: Move Blizzard declarations into a new header
Add an entries the Blizzard device in MAINTAINERS.
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e8fa395881c3b07069f142ea51c38b31b885baa0
https://github.com/qemu/qemu/commit/e8fa395881c3b07069f142ea51c38b31b885baa0
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M MAINTAINERS
M hw/arm/nseries.c
M hw/misc/cbus.c
M include/hw/devices.h
A include/hw/misc/cbus.h
Log Message:
-----------
hw/devices: Move CBus declarations into a new header
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 98fa33276e2b5be5beb549d801bbac4b0b2db119
https://github.com/qemu/qemu/commit/98fa33276e2b5be5beb549d801bbac4b0b2db119
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M MAINTAINERS
M hw/arm/stellaris.c
M hw/input/stellaris_input.c
M include/hw/devices.h
A include/hw/input/gamepad.h
Log Message:
-----------
hw/devices: Move Gamepad declarations into a new header
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: a331dd029911fa85fd2e9fa72101396cd5b5fc08
https://github.com/qemu/qemu/commit/a331dd029911fa85fd2e9fa72101396cd5b5fc08
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M MAINTAINERS
M hw/arm/nseries.c
M hw/arm/palm.c
M hw/input/tsc2005.c
M hw/input/tsc210x.c
M include/hw/arm/omap.h
M include/hw/devices.h
A include/hw/input/tsc2xxx.h
M include/qemu/typedefs.h
Log Message:
-----------
hw/devices: Move TI touchscreen declarations into a new header
Since uWireSlave is only used in this new header, there is no
need to expose it via "qemu/typedefs.h".
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 66b03dcec2715ffb3bc121114650502c9d3ffaef
https://github.com/qemu/qemu/commit/66b03dcec2715ffb3bc121114650502c9d3ffaef
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/arm/kzm.c
M hw/arm/mps2.c
M hw/arm/realview.c
M hw/arm/vexpress.c
M hw/net/lan9118.c
M include/hw/devices.h
A include/hw/net/lan9118.h
Log Message:
-----------
hw/devices: Move LAN9118 declarations into a new header
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e7a3c55a95ba3d091903624d4934f8be34ff4315
https://github.com/qemu/qemu/commit/e7a3c55a95ba3d091903624d4934f8be34ff4315
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M include/hw/net/ne2000-isa.h
Log Message:
-----------
hw/net/ne2000-isa: Add guards to the header
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 94630665b5b04235400a7bb6236539b2593eff35
https://github.com/qemu/qemu/commit/94630665b5b04235400a7bb6236539b2593eff35
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/arm/exynos4_boards.c
M hw/arm/mps2-tz.c
M hw/net/lan9118.c
M include/hw/net/lan9118.h
Log Message:
-----------
hw/net/lan9118: Export TYPE_LAN9118 and use it instead of hardcoded string
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 437cc27ddfded3bbab6afd5ac1761e0e195edba7
https://github.com/qemu/qemu/commit/437cc27ddfded3bbab6afd5ac1761e0e195edba7
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M hw/arm/gumstix.c
M hw/arm/integratorcp.c
M hw/arm/mainstone.c
M hw/arm/realview.c
M hw/arm/versatilepb.c
M hw/net/smc91c111.c
R include/hw/devices.h
A include/hw/net/smc91c111.h
Log Message:
-----------
hw/devices: Move SMSC 91C111 declaration into a new header
This commit finally deletes "hw/devices.h".
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 82b2865e0d0ea4c1001e9e7ed7920bcc0458f6de
https://github.com/qemu/qemu/commit/82b2865e0d0ea4c1001e9e7ed7920bcc0458f6de
Author: Peter Maydell <address@hidden>
Date: 2019-04-29 (Mon, 29 Apr 2019)
Changed paths:
M MAINTAINERS
M configure
M hw/arm/aspeed.c
M hw/arm/exynos4_boards.c
M hw/arm/gumstix.c
M hw/arm/integratorcp.c
M hw/arm/kzm.c
M hw/arm/mainstone.c
M hw/arm/mps2-tz.c
M hw/arm/mps2.c
M hw/arm/nseries.c
M hw/arm/palm.c
M hw/arm/realview.c
M hw/arm/smmu-common.c
M hw/arm/smmuv3.c
M hw/arm/stellaris.c
M hw/arm/tosa.c
M hw/arm/versatilepb.c
M hw/arm/vexpress.c
M hw/display/blizzard.c
M hw/display/tc6393xb.c
M hw/dma/Makefile.objs
M hw/input/stellaris_input.c
M hw/input/tsc2005.c
M hw/input/tsc210x.c
M hw/intc/armv7m_nvic.c
M hw/misc/cbus.c
M hw/net/lan9118.c
M hw/net/smc91c111.c
M hw/ssi/xilinx_spips.c
M include/hw/arm/omap.h
M include/hw/arm/smmu-common.h
R include/hw/devices.h
A include/hw/display/blizzard.h
A include/hw/display/tc6393xb.h
A include/hw/input/gamepad.h
A include/hw/input/tsc2xxx.h
A include/hw/misc/cbus.h
A include/hw/net/lan9118.h
M include/hw/net/ne2000-isa.h
A include/hw/net/smc91c111.h
M include/qemu/typedefs.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/machine.c
M target/arm/translate.c
M target/arm/translate.h
M target/arm/vfp_helper.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190429'
into staging
target-arm queue:
* remove "bag of random stuff" hw/devices.h header
* implement FPU for Cortex-M and enable it for Cortex-M4 and -M33
* hw/dma: Compile the bcm2835_dma device as common object
* configure: Remove --source-path option
* hw/ssi/xilinx_spips: Avoid variable length array
* hw/arm/smmuv3: Remove SMMUNotifierNode
# gpg: Signature made Mon 29 Apr 2019 17:58:57 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190429: (42 commits)
hw/devices: Move SMSC 91C111 declaration into a new header
hw/net/lan9118: Export TYPE_LAN9118 and use it instead of hardcoded string
hw/net/ne2000-isa: Add guards to the header
hw/devices: Move LAN9118 declarations into a new header
hw/devices: Move TI touchscreen declarations into a new header
hw/devices: Move Gamepad declarations into a new header
hw/devices: Move CBus declarations into a new header
hw/devices: Move Blizzard declarations into a new header
hw/devices: Move TC6393XB declarations into a new header
hw/display/tc6393xb: Remove unused functions
hw/arm/nseries: Use TYPE_TMP105 instead of hardcoded string
hw/arm/aspeed: Use TYPE_TMP105/TYPE_PCA9552 instead of hardcoded string
hw/dma: Compile the bcm2835_dma device as common object
target/arm: Enable FPU for Cortex-M4 and Cortex-M33
target/arm: Implement VLLDM for v7M CPUs with an FPU
target/arm: Implement VLSTM for v7M CPUs with an FPU
target/arm: Implement M-profile lazy FP state preservation
target/arm: Add lazy-FP-stacking support to v7m_stack_write()
target/arm: New function armv7m_nvic_set_pending_lazyfp()
target/arm: New helper function arm_v7m_mmu_idx_all()
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/413a99a92c13...82b2865e0d0e
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