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[Qemu-commits] [qemu/qemu] 67d803: hw/intc/bcm2836_control: Implement lo
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] 67d803: hw/intc/bcm2836_control: Implement local timer |
Date: |
Fri, 15 Mar 2019 12:28:36 +0000 (UTC) |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 67d80321f26d9ea2b623ffac567a2f758ceae037
https://github.com/qemu/qemu/commit/67d80321f26d9ea2b623ffac567a2f758ceae037
Author: Zoltán Baldaszti <address@hidden>
Date: 2019-03-15 (Fri, 15 Mar 2019)
Changed paths:
M hw/intc/bcm2836_control.c
M include/hw/intc/bcm2836_control.h
Log Message:
-----------
hw/intc/bcm2836_control: Implement local timer
The BCM2836 control logic module includes a simple
"local timer" which is a programmable down-counter that
can generates an interrupt. Implement this functionality.
Signed-off-by: Zoltán Baldaszti <address@hidden>
[PMM: wrote commit message; wrapped long line; tweaked
some comments to match the final version of the code]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 41c4fb94aa8a6a16bd107687cd3b5204c68a4042
https://github.com/qemu/qemu/commit/41c4fb94aa8a6a16bd107687cd3b5204c68a4042
Author: Eric Auger <address@hidden>
Date: 2019-03-15 (Fri, 15 Mar 2019)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt-acpi-build: Fix SMMUv3 GSIV values
The GSIV numbers of the SPI based interrupts is not correct as
ARM_SPI_BASE was not added to the irqmap[VIRT_SMMU] value. So
this may collide with VIRTIO_MMIO irq window.
Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Reviewed-by: Shannon Zhao <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: daf1dc5f82cefe2a57f184d5053e8b274ad2ba9a
https://github.com/qemu/qemu/commit/daf1dc5f82cefe2a57f184d5053e8b274ad2ba9a
Author: Dongjiu Geng <address@hidden>
Date: 2019-03-15 (Fri, 15 Mar 2019)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: change arch timer registers access permission
Some generic arch timer registers are Config-RW in the EL0,
which means the EL0 exception level can have write permission
if it is appropriately configured.
When VM access registers, QEMU firstly checks whether they have RW
permission, then check whether it is appropriately configured.
If they are defined to read only in EL0, even though they have been
appropriately configured, they still do not have write permission.
So need to add the write permission according to ARMV8 spec when
define it.
Signed-off-by: Dongjiu Geng <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: deb224bc72287383655f86a13b934477c1e5c10d
https://github.com/qemu/qemu/commit/deb224bc72287383655f86a13b934477c1e5c10d
Author: Wei Yang <address@hidden>
Date: 2019-03-15 (Fri, 15 Mar 2019)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt-acpi-build: use PCIE_MMCFG_BUS to retrieve end_bus_number
This is more proper to use PCIE_MMCFG_BUS to retrieve end_bus_number.
Signed-off-by: Wei Yang <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5de56742a3c91de3d646326bec43a989bba83ca4
https://github.com/qemu/qemu/commit/5de56742a3c91de3d646326bec43a989bba83ca4
Author: Amir Charif <address@hidden>
Date: 2019-03-15 (Fri, 15 Mar 2019)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Check access permission to ADDVL/ADDPL/RDVL
These instructions do not trap when SVE is disabled in EL0,
causing them to be executed with wrong size information.
Signed-off-by: Amir Charif <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
[PMM: added 'target/arm' prefix to subject]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8b088d3f8ab5642020d28fa0c2a8d938bc5f3592
https://github.com/qemu/qemu/commit/8b088d3f8ab5642020d28fa0c2a8d938bc5f3592
Author: Peter Maydell <address@hidden>
Date: 2019-03-15 (Fri, 15 Mar 2019)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/intc/bcm2836_control.c
M include/hw/intc/bcm2836_control.h
M target/arm/helper.c
M target/arm/translate-sve.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190315'
into staging
target-arm queue:
* Add missing SVE-enabled check to ADDVL/ADDPL/RDVL
* virt-acpi-build: use PCIE_MMCFG_BUS to retrieve end_bus_number
* virt-acpi-build: Fix SMMUv3 GSIV values
* Allow EL0 to write to arch timer registers, not just read them
* bcm2836_control: Implement local timer
# gpg: Signature made Fri 15 Mar 2019 11:37:29 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190315:
target/arm: Check access permission to ADDVL/ADDPL/RDVL
hw/arm/virt-acpi-build: use PCIE_MMCFG_BUS to retrieve end_bus_number
target/arm: change arch timer registers access permission
hw/arm/virt-acpi-build: Fix SMMUv3 GSIV values
hw/intc/bcm2836_control: Implement local timer
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/7074ab12c81a...8b088d3f8ab5
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