[Qemu-commits] [qemu/qemu] 2a53cf: target/riscv: Activate decodetree and

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[Qemu-commits] [qemu/qemu] 2a53cf: target/riscv: Activate decodetree and

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 2a53cf: target/riscv: Activate decodetree and implemnt LUI...
Date:	Thu, 14 Mar 2019 00:42:36 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 2a53cff418335ccb4719e9a94fde55f6ebcc895d
      
https://github.com/qemu/qemu/commit/2a53cff418335ccb4719e9a94fde55f6ebcc895d
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/Makefile.objs
    A target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Activate decodetree and implemnt LUI & AUIPC

for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.

Reviewed-by: Richard Henderson <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 3cca75a6fe8b3f85e19559ffa64cb0be370d2814
      
https://github.com/qemu/qemu/commit/3cca75a6fe8b3f85e19559ffa64cb0be370d2814
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RVXI branch insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: c1000d4e1bdb13857b601c425aca2fda9131283b
      
https://github.com/qemu/qemu/commit/c1000d4e1bdb13857b601c425aca2fda9131283b
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvi.inc.c

  Log Message:
  -----------
  target/riscv: Convert RV32I load/store insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 7e45a682edc32ba90d6955215f062210531b835b
      
https://github.com/qemu/qemu/commit/7e45a682edc32ba90d6955215f062210531b835b
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/Makefile.objs
    A target/riscv/insn32-64.decode
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RV64I load/store insns to decodetree

this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: b73a987b09ad5081123dc6b1e8e6c8305a1c8673
      
https://github.com/qemu/qemu/commit/b73a987b09ad5081123dc6b1e8e6c8305a1c8673
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32-64.decode
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RVXI arithmetic insns to decodetree

we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 0c865e856a7e97d37c4dea4cf2ff875faa6e72ed
      
https://github.com/qemu/qemu/commit/0c865e856a7e97d37c4dea4cf2ff875faa6e72ed
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RVXI fence insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 771fbe156a2a2be964a4fbe6251339a5570a26c4
      
https://github.com/qemu/qemu/commit/771fbe156a2a2be964a4fbe6251339a5570a26c4
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RVXI csr insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: d2e2c1e406e0ab886eafeb012fd2ed0d21f3a6a1
      
https://github.com/qemu/qemu/commit/d2e2c1e406e0ab886eafeb012fd2ed0d21f3a6a1
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32-64.decode
    M target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_rvm.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RVXM insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 3b77c289aef21b33517f2fd7639cce13bed50cc1
      
https://github.com/qemu/qemu/commit/3b77c289aef21b33517f2fd7639cce13bed50cc1
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_rva.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RV32A insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 40b9faecfe8000520958f50a77ea16f4b3dd6405
      
https://github.com/qemu/qemu/commit/40b9faecfe8000520958f50a77ea16f4b3dd6405
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32-64.decode
    M target/riscv/insn_trans/trans_rva.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RV64A insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 6f0e74ff4b7f83901e99e59108eaa43513a0ce36
      
https://github.com/qemu/qemu/commit/6f0e74ff4b7f83901e99e59108eaa43513a0ce36
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_rvf.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RV32F insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 95561ee3b41a536cc373e59da10605e2a8676ee2
      
https://github.com/qemu/qemu/commit/95561ee3b41a536cc373e59da10605e2a8676ee2
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32-64.decode
    M target/riscv/insn_trans/trans_rvf.inc.c

  Log Message:
  -----------
  target/riscv: Convert RV64F insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 97f8b49372d73aab4d172df4ea297d7f3ce4e02e
      
https://github.com/qemu/qemu/commit/97f8b49372d73aab4d172df4ea297d7f3ce4e02e
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_rvd.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RV32D insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 31fe4d35f2608daecb2319c81e0bb4af81b398ae
      
https://github.com/qemu/qemu/commit/31fe4d35f2608daecb2319c81e0bb4af81b398ae
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32-64.decode
    M target/riscv/insn_trans/trans_rvd.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RV64D insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 4ba79c47a205b3af4b62b9b1b6090dee678a1069
      
https://github.com/qemu/qemu/commit/4ba79c47a205b3af4b62b9b1b6090dee678a1069
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_privileged.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert RV priv insns to decodetree

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: e98d9140f27890ebd27bb7e9e216a8ea0d53f2ce
      
https://github.com/qemu/qemu/commit/e98d9140f27890ebd27bb7e9e216a8ea0d53f2ce
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/Makefile.objs
    A target/riscv/insn16.decode
    A target/riscv/insn_trans/trans_rvc.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert quadrant 0 of RVXC insns to decodetree

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 07b001c6fc500fa0e87fd8210f270d7dc8aff9ea
      
https://github.com/qemu/qemu/commit/07b001c6fc500fa0e87fd8210f270d7dc8aff9ea
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn16.decode
    M target/riscv/insn_trans/trans_rvc.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert quadrant 1 of RVXC insns to decodetree

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 97b0be81f6f20bfd53725cb2500b47c6786be532
      
https://github.com/qemu/qemu/commit/97b0be81f6f20bfd53725cb2500b47c6786be532
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn16.decode
    M target/riscv/insn_trans/trans_rvc.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Convert quadrant 2 of RVXC insns to decodetree

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 9e92c57d834cd50ab088d75510c3c720878eef13
      
https://github.com/qemu/qemu/commit/9e92c57d834cd50ab088d75510c3c720878eef13
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove gen_jalr()

trans_jalr() is the only caller, so move the code into trans_jalr().

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 090cc2c898a04e42350eabf1bcf7d245471603f9
      
https://github.com/qemu/qemu/commit/090cc2c898a04e42350eabf1bcf7d245471603f9
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove manual decoding from gen_branch()

We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 98898b20e9cca462843c22ad952c216ffd57d654
      
https://github.com/qemu/qemu/commit/98898b20e9cca462843c22ad952c216ffd57d654
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove manual decoding from gen_load()

With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: bce8a342a1f0919479d18ec812b100136daa746b
      
https://github.com/qemu/qemu/commit/bce8a342a1f0919479d18ec812b100136daa746b
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove manual decoding from gen_store()

With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 7a50d3e2ae7f13b24fe55990ea0b8ddcbbb43130
      
https://github.com/qemu/qemu/commit/7a50d3e2ae7f13b24fe55990ea0b8ddcbbb43130
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Move gen_arith_imm() decoding into trans_* functions

gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: f2ab1728675772cd475a33f4df3d2f68a22c188f
      
https://github.com/qemu/qemu/commit/f2ab1728675772cd475a33f4df3d2f68a22c188f
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists

manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 34446e845829f55eaa9a07a915950af0b2710b47
      
https://github.com/qemu/qemu/commit/34446e845829f55eaa9a07a915950af0b2710b47
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove shift and slt insn manual decoding

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 1288701682d81b93f62e01cd87001dc90b30b881
      
https://github.com/qemu/qemu/commit/1288701682d81b93f62e01cd87001dc90b30b881
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn_trans/trans_rvm.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove manual decoding of RV32/64M insn

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 8dc9e8a8b04c4308cf275aa6480d289dcd3cf9b3
      
https://github.com/qemu/qemu/commit/8dc9e8a8b04c4308cf275aa6480d289dcd3cf9b3
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/insn_trans/trans_rvm.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Rename trans_arith to gen_arith

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>


  Commit: 8f7bc273868939f0821e07fb23792db63d45bffb
      
https://github.com/qemu/qemu/commit/8f7bc273868939f0821e07fb23792db63d45bffb
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove gen_system()

with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 25e6ca30c668783cd72ff97080ff44e141b99f9b
      
https://github.com/qemu/qemu/commit/25e6ca30c668783cd72ff97080ff44e141b99f9b
  Author: Bastian Koppelmann <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove decode_RV32_64G()

decodetree handles all instructions now so the fallback is not necessary
anymore.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>


  Commit: 1fa87eb56ea0af5a8133b9e11101732f5df7d46f
      
https://github.com/qemu/qemu/commit/1fa87eb56ea0af5a8133b9e11101732f5df7d46f
  Author: Peter Maydell <address@hidden>
  Date:   2019-03-13 (Wed, 13 Mar 2019)

  Changed paths:
    M target/riscv/Makefile.objs
    A target/riscv/insn16.decode
    A target/riscv/insn32-64.decode
    A target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_privileged.inc.c
    A target/riscv/insn_trans/trans_rva.inc.c
    A target/riscv/insn_trans/trans_rvc.inc.c
    A target/riscv/insn_trans/trans_rvd.inc.c
    A target/riscv/insn_trans/trans_rvf.inc.c
    A target/riscv/insn_trans/trans_rvi.inc.c
    A target/riscv/insn_trans/trans_rvm.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' 
into staging

target/riscv: Convert to decodetree

Bastian: this patchset converts the RISC-V decoder to decodetree in four major 
steps:

1) Convert 32-bit instructions to decodetree [Patch 1-15]:
    Many of the gen_* functions are called by the decode functions for 16-bit
    and 32-bit functions. If we move translation code from the gen_*
    functions to the generated trans_* functions of decode-tree, we get a lot of
    duplication. Therefore, we mostly generate calls to the old gen_* function
    which are properly replaced after step 2).

    Each of the trans_ functions are grouped into files corresponding to their
    ISA extension, e.g. addi which is in RV32I is translated in the file
    'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 16-18]:
    All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
    we convert the arguments in the 16 bit trans_ function to the arguments of
    the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 19-29]:
    this move all manual translation code into the trans_* instructions of
    decode tree, such that we can remove the old decode_* functions.

Palmer: This, with some additional cleanup patches, passed Alistar's
testing on rv32 and rv64 as well as my testing on rv64, so I think it's
good to go.  I've run my standard test against this exact tag.

I still don't have a Mac to try this on, sorry!

# gpg: Signature made Wed 13 Mar 2019 13:44:49 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.0-sf4: (29 commits)
  target/riscv: Remove decode_RV32_64G()
  target/riscv: Remove gen_system()
  target/riscv: Rename trans_arith to gen_arith
  target/riscv: Remove manual decoding of RV32/64M insn
  target/riscv: Remove shift and slt insn manual decoding
  target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
  target/riscv: Move gen_arith_imm() decoding into trans_* functions
  target/riscv: Remove manual decoding from gen_store()
  target/riscv: Remove manual decoding from gen_load()
  target/riscv: Remove manual decoding from gen_branch()
  target/riscv: Remove gen_jalr()
  target/riscv: Convert quadrant 2 of RVXC insns to decodetree
  target/riscv: Convert quadrant 1 of RVXC insns to decodetree
  target/riscv: Convert quadrant 0 of RVXC insns to decodetree
  target/riscv: Convert RV priv insns to decodetree
  target/riscv: Convert RV64D insns to decodetree
  target/riscv: Convert RV32D insns to decodetree
  target/riscv: Convert RV64F insns to decodetree
  target/riscv: Convert RV32F insns to decodetree
  target/riscv: Convert RV64A insns to decodetree
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/85ce84489a74...1fa87eb56ea0
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